161 lines
3.7 KiB
C
161 lines
3.7 KiB
C
/*
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* Copyright (c) 2021 Synopsys
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT snps_creg_gpio
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#include <errno.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/i2c.h>
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#include <zephyr/sys/byteorder.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(creg_gpio, CONFIG_GPIO_LOG_LEVEL);
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#include "gpio_utils.h"
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/** Runtime driver data */
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struct creg_gpio_drv_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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uint32_t pin_val;
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uint32_t base_addr;
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};
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/** Configuration data */
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struct creg_gpio_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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uint32_t ngpios;
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uint8_t bit_per_gpio;
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uint8_t off_val;
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uint8_t on_val;
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};
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static int pin_config(const struct device *dev,
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gpio_pin_t pin,
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gpio_flags_t flags)
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{
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return -ENOTSUP;
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}
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static int port_get(const struct device *dev,
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gpio_port_value_t *value)
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{
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const struct creg_gpio_config *cfg = dev->config;
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struct creg_gpio_drv_data *drv_data = dev->data;
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uint32_t in = sys_read32(drv_data->base_addr);
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uint32_t tmp = 0;
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uint32_t val = 0;
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for (uint8_t i = 0; i < cfg->ngpios; i++) {
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tmp = (in & cfg->on_val << i * cfg->bit_per_gpio) ? 1 : 0;
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val |= tmp << i;
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}
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*value = drv_data->pin_val = val;
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return 0;
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}
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static int port_write(const struct device *dev,
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gpio_port_pins_t mask,
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gpio_port_value_t value,
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gpio_port_value_t toggle)
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{
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const struct creg_gpio_config *cfg = dev->config;
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struct creg_gpio_drv_data *drv_data = dev->data;
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uint32_t *pin_val = &drv_data->pin_val;
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uint32_t out = 0;
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uint32_t tmp = 0;
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*pin_val = ((*pin_val & ~mask) | (value & mask)) ^ toggle;
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for (uint8_t i = 0; i < cfg->ngpios; i++) {
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tmp = (*pin_val & 1 << i) ? cfg->on_val : cfg->off_val;
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out |= tmp << i * cfg->bit_per_gpio;
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}
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sys_write32(out, drv_data->base_addr);
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return 0;
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}
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static int port_set_masked(const struct device *dev,
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gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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return port_write(dev, mask, value, 0);
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}
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static int port_set_bits(const struct device *dev,
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gpio_port_pins_t pins)
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{
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return port_write(dev, pins, pins, 0);
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}
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static int port_clear_bits(const struct device *dev,
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gpio_port_pins_t pins)
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{
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return port_write(dev, pins, 0, 0);
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}
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static int port_toggle_bits(const struct device *dev,
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gpio_port_pins_t pins)
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{
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return port_write(dev, 0, 0, pins);
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}
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static int pin_interrupt_configure(const struct device *dev,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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return -ENOTSUP;
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}
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/**
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* @brief Initialization function of creg_gpio
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*
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* @param dev Device struct
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* @return 0 if successful, failed otherwise.
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*/
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static int creg_gpio_init(const struct device *dev)
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{
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return 0;
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}
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static const struct gpio_driver_api api_table = {
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.pin_configure = pin_config,
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.port_get_raw = port_get,
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.port_set_masked_raw = port_set_masked,
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.port_set_bits_raw = port_set_bits,
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.port_clear_bits_raw = port_clear_bits,
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.port_toggle_bits = port_toggle_bits,
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.pin_interrupt_configure = pin_interrupt_configure,
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};
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static const struct creg_gpio_config creg_gpio_cfg = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(0),
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},
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.ngpios = DT_INST_PROP(0, ngpios),
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.bit_per_gpio = DT_INST_PROP(0, bit_per_gpio),
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.off_val = DT_INST_PROP(0, off_val),
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.on_val = DT_INST_PROP(0, on_val),
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};
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static struct creg_gpio_drv_data creg_gpio_drvdata = {
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.base_addr = DT_INST_REG_ADDR(0),
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};
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DEVICE_DT_INST_DEFINE(0, creg_gpio_init, NULL,
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&creg_gpio_drvdata, &creg_gpio_cfg,
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POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY,
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&api_table);
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