208 lines
5.3 KiB
C
208 lines
5.3 KiB
C
/*
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* Copyright (c) 2020 Mohamed ElShahawi.
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* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT espressif_esp32_rtc
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#define CPU_RESET_REASON RTC_SW_CPU_RESET
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#ifdef CONFIG_SOC_ESP32
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#define DT_CPU_COMPAT cdns_tensilica_xtensa_lx6
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#undef CPU_RESET_REASON
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#define CPU_RESET_REASON SW_CPU_RESET
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#include <zephyr/dt-bindings/clock/esp32_clock.h>
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#include "esp32/rom/rtc.h"
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#include "soc/dport_reg.h"
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#elif defined(CONFIG_SOC_ESP32S2)
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#define DT_CPU_COMPAT cdns_tensilica_xtensa_lx7
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#include <zephyr/dt-bindings/clock/esp32s2_clock.h>
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#include "esp32s2/rom/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32C3
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#define DT_CPU_COMPAT espressif_riscv
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#include <zephyr/dt-bindings/clock/esp32c3_clock.h>
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#include "esp32c3/rom/rtc.h"
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#include <soc/soc_caps.h>
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#include <soc/soc.h>
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#include <soc/rtc.h>
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#endif
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#include <soc/rtc.h>
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#include <soc/apb_ctrl_reg.h>
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#include <soc/timer_group_reg.h>
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#include <hal/clk_gate_ll.h>
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#include <soc.h>
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#include <zephyr/drivers/clock_control.h>
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#include <driver/periph_ctrl.h>
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#include <hal/cpu_hal.h>
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struct esp32_clock_config {
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int clk_src_sel;
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uint32_t cpu_freq;
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uint32_t xtal_freq_sel;
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int xtal_div;
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};
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static uint8_t const xtal_freq[] = {
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#ifdef CONFIG_SOC_ESP32
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[ESP32_CLK_XTAL_24M] = 24,
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[ESP32_CLK_XTAL_26M] = 26,
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[ESP32_CLK_XTAL_40M] = 40,
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[ESP32_CLK_XTAL_AUTO] = 0
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#elif defined(CONFIG_SOC_ESP32S2)
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[ESP32_CLK_XTAL_40M] = 40,
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#elif defined(CONFIG_SOC_ESP32C3)
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[ESP32_CLK_XTAL_32M] = 32,
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[ESP32_CLK_XTAL_40M] = 40,
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#endif
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};
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static int clock_control_esp32_on(const struct device *dev,
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clock_control_subsys_t sys)
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{
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ARG_UNUSED(dev);
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periph_module_enable((periph_module_t)sys);
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return 0;
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}
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static int clock_control_esp32_off(const struct device *dev,
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clock_control_subsys_t sys)
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{
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ARG_UNUSED(dev);
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periph_module_disable((periph_module_t)sys);
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return 0;
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}
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static int clock_control_esp32_async_on(const struct device *dev,
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clock_control_subsys_t sys,
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clock_control_cb_t cb,
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void *user_data)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(sys);
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ARG_UNUSED(cb);
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ARG_UNUSED(user_data);
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return -ENOTSUP;
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}
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static enum clock_control_status clock_control_esp32_get_status(const struct device *dev,
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clock_control_subsys_t sys)
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{
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ARG_UNUSED(dev);
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uint32_t clk_en_reg = periph_ll_get_clk_en_reg((periph_module_t)sys);
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uint32_t clk_en_mask = periph_ll_get_clk_en_mask((periph_module_t)sys);
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if (DPORT_GET_PERI_REG_MASK(clk_en_reg, clk_en_mask)) {
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return CLOCK_CONTROL_STATUS_ON;
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}
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return CLOCK_CONTROL_STATUS_OFF;
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}
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static int clock_control_esp32_get_rate(const struct device *dev,
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clock_control_subsys_t sub_system,
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uint32_t *rate)
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{
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ARG_UNUSED(sub_system);
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rtc_cpu_freq_config_t config;
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rtc_clk_cpu_freq_get_config(&config);
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*rate = config.freq_mhz;
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return 0;
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}
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static int clock_control_esp32_init(const struct device *dev)
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{
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const struct esp32_clock_config *cfg = dev->config;
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rtc_cpu_freq_config_t old_config;
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rtc_cpu_freq_config_t new_config;
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bool res;
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/* reset default config to use dts config */
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if (rtc_clk_apb_freq_get() < APB_CLK_FREQ || rtc_get_reset_reason(0) != CPU_RESET_REASON) {
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rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT();
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clk_cfg.xtal_freq = xtal_freq[cfg->xtal_freq_sel];
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clk_cfg.cpu_freq_mhz = cfg->cpu_freq;
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clk_cfg.slow_freq = rtc_clk_slow_freq_get();
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clk_cfg.fast_freq = rtc_clk_fast_freq_get();
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rtc_clk_init(clk_cfg);
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}
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rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M);
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rtc_clk_cpu_freq_get_config(&old_config);
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const uint32_t old_freq_mhz = old_config.freq_mhz;
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const uint32_t new_freq_mhz = cfg->cpu_freq;
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res = rtc_clk_cpu_freq_mhz_to_config(cfg->cpu_freq, &new_config);
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if (!res) {
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return -ENOTSUP;
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}
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/* wait uart output to be cleared */
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esp_rom_uart_tx_wait_idle(0);
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if (cfg->xtal_div >= 0) {
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new_config.div = cfg->xtal_div;
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}
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if (cfg->clk_src_sel >= 0) {
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new_config.source = cfg->clk_src_sel;
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}
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/* set new configuration */
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rtc_clk_cpu_freq_set_config(&new_config);
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/* Re-calculate the ccount to make time calculation correct */
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cpu_hal_set_cycle_count((uint64_t)cpu_hal_get_cycle_count() * new_freq_mhz / old_freq_mhz);
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/* Enable RNG clock. */
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periph_module_enable(PERIPH_RNG_MODULE);
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return 0;
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}
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static const struct clock_control_driver_api clock_control_esp32_api = {
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.on = clock_control_esp32_on,
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.off = clock_control_esp32_off,
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.async_on = clock_control_esp32_async_on,
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.get_rate = clock_control_esp32_get_rate,
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.get_status = clock_control_esp32_get_status,
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};
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#define ESP32_CLOCK_SOURCE \
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COND_CODE_1(DT_NODE_HAS_PROP(DT_INST(0, DT_CPU_COMPAT), clock_source), \
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(DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_source)), (-1))
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#define ESP32_CLOCK_XTAL_DIV \
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COND_CODE_1(DT_NODE_HAS_PROP(0, xtal_div), \
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(DT_INST_PROP(0, xtal_div)), (-1))
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static const struct esp32_clock_config esp32_clock_config0 = {
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.clk_src_sel = ESP32_CLOCK_SOURCE,
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.cpu_freq = DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_frequency),
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.xtal_freq_sel = DT_INST_PROP(0, xtal_freq),
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.xtal_div = ESP32_CLOCK_XTAL_DIV
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};
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DEVICE_DT_DEFINE(DT_NODELABEL(rtc),
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&clock_control_esp32_init,
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NULL,
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NULL,
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&esp32_clock_config0,
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PRE_KERNEL_1,
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
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&clock_control_esp32_api);
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#ifndef CONFIG_SOC_ESP32C3
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BUILD_ASSERT((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) ==
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MHZ(DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_frequency)),
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"SYS_CLOCK_HW_CYCLES_PER_SEC Value must be equal to CPU_Freq");
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#endif
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