50 lines
1.0 KiB
C
50 lines
1.0 KiB
C
/*
|
|
* Copyright (c) 2018 Linaro Limited
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
/**
|
|
* @file
|
|
* @brief System/hardware module for STM32WB processor
|
|
*/
|
|
|
|
#include <zephyr/device.h>
|
|
#include <zephyr/init.h>
|
|
#include <zephyr/logging/log.h>
|
|
|
|
#include <stm32_ll_system.h>
|
|
|
|
#include <cmsis_core.h>
|
|
|
|
#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
|
|
LOG_MODULE_REGISTER(soc);
|
|
|
|
/**
|
|
* @brief Perform basic hardware initialization at boot.
|
|
*
|
|
* This needs to be run from the very beginning.
|
|
* So the init priority has to be 0 (zero).
|
|
*
|
|
* @return 0
|
|
*/
|
|
static int stm32wb_init(void)
|
|
{
|
|
/* Enable the ART Accelerator I-cache, D-cache and prefetch */
|
|
LL_FLASH_EnableInstCache();
|
|
LL_FLASH_EnableDataCache();
|
|
LL_FLASH_EnablePrefetch();
|
|
|
|
/* Update CMSIS SystemCoreClock variable (HCLK) */
|
|
/* At reset, system core clock is set to 4 MHz from MSI */
|
|
SystemCoreClock = 4000000;
|
|
|
|
/* Set C2 Power Mode to shutdown */
|
|
/* It will be updated by C2 when required */
|
|
LL_C2_PWR_SetPowerMode(LL_PWR_MODE_SHUTDOWN);
|
|
|
|
return 0;
|
|
}
|
|
|
|
SYS_INIT(stm32wb_init, PRE_KERNEL_1, 0);
|