708 lines
16 KiB
C
708 lines
16 KiB
C
/*
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* Copyright (c) 2021 BrainCo Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT gd_gd32_i2c
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#include <errno.h>
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#include <zephyr/kernel.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/i2c.h>
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#include <gd32_i2c.h>
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#include <gd32_rcu.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(i2c_gd32, CONFIG_I2C_LOG_LEVEL);
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#include "i2c-priv.h"
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/* Bus error */
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#define I2C_GD32_ERR_BERR BIT(0)
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/* Arbitration lost */
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#define I2C_GD32_ERR_LARB BIT(1)
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/* No ACK received */
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#define I2C_GD32_ERR_AERR BIT(2)
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/* I2C bus busy */
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#define I2C_GD32_ERR_BUSY BIT(4)
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struct i2c_gd32_config {
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uint32_t reg;
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uint32_t bitrate;
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uint32_t rcu_periph_clock;
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const struct pinctrl_dev_config *pcfg;
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void (*irq_cfg_func)(void);
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};
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struct i2c_gd32_data {
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struct k_sem bus_mutex;
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struct k_sem sync_sem;
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uint32_t dev_config;
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uint16_t addr1;
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uint16_t addr2;
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uint32_t xfer_len;
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struct i2c_msg *current;
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uint8_t errs;
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bool is_restart;
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};
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static inline void i2c_gd32_enable_interrupts(const struct i2c_gd32_config *cfg)
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{
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I2C_CTL1(cfg->reg) |= I2C_CTL1_ERRIE;
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I2C_CTL1(cfg->reg) |= I2C_CTL1_EVIE;
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I2C_CTL1(cfg->reg) |= I2C_CTL1_BUFIE;
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}
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static inline void i2c_gd32_disable_interrupts(const struct i2c_gd32_config *cfg)
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{
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I2C_CTL1(cfg->reg) &= ~I2C_CTL1_ERRIE;
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I2C_CTL1(cfg->reg) &= ~I2C_CTL1_EVIE;
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I2C_CTL1(cfg->reg) &= ~I2C_CTL1_BUFIE;
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}
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static inline void i2c_gd32_xfer_read(struct i2c_gd32_data *data,
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const struct i2c_gd32_config *cfg)
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{
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data->current->len--;
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*data->current->buf = I2C_DATA(cfg->reg);
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data->current->buf++;
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if ((data->xfer_len > 0U) &&
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(data->current->len == 0U)) {
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data->current++;
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}
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}
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static inline void i2c_gd32_xfer_write(struct i2c_gd32_data *data,
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const struct i2c_gd32_config *cfg)
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{
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data->current->len--;
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I2C_DATA(cfg->reg) = *data->current->buf;
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data->current->buf++;
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if ((data->xfer_len > 0U) &&
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(data->current->len == 0U)) {
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data->current++;
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}
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}
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static void i2c_gd32_handle_rbne(const struct device *dev)
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{
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struct i2c_gd32_data *data = dev->data;
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const struct i2c_gd32_config *cfg = dev->config;
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switch (data->xfer_len) {
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case 0:
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/* Unwanted data received, ignore it. */
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k_sem_give(&data->sync_sem);
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break;
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case 1:
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/* If total_read_length == 1, read the data directly. */
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data->xfer_len--;
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i2c_gd32_xfer_read(data, cfg);
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k_sem_give(&data->sync_sem);
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break;
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case 2:
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__fallthrough;
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case 3:
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/*
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* If total_read_length == 2, or total_read_length > 3
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* and remaining_read_length == 3, disable the RBNE
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* interrupt.
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* Remaining data will be read from BTC interrupt.
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*/
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I2C_CTL1(cfg->reg) &= ~I2C_CTL1_BUFIE;
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break;
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default:
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/*
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* If total_read_length > 3 and remaining_read_length > 3,
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* read the data directly.
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*/
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data->xfer_len--;
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i2c_gd32_xfer_read(data, cfg);
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break;
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}
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}
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static void i2c_gd32_handle_tbe(const struct device *dev)
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{
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struct i2c_gd32_data *data = dev->data;
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const struct i2c_gd32_config *cfg = dev->config;
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if (data->xfer_len > 0U) {
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data->xfer_len--;
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if (data->xfer_len == 0U) {
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/*
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* This is the last data to transmit, disable the TBE interrupt.
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* Use the BTC interrupt to indicate the write data complete state.
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*/
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I2C_CTL1(cfg->reg) &= ~I2C_CTL1_BUFIE;
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}
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i2c_gd32_xfer_write(data, cfg);
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} else {
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/* Enter stop condition */
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I2C_CTL0(cfg->reg) |= I2C_CTL0_STOP;
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k_sem_give(&data->sync_sem);
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}
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}
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static void i2c_gd32_handle_btc(const struct device *dev)
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{
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struct i2c_gd32_data *data = dev->data;
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const struct i2c_gd32_config *cfg = dev->config;
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if (data->current->flags & I2C_MSG_READ) {
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uint32_t counter = 0U;
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switch (data->xfer_len) {
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case 2:
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/* Stop condition must be generated before reading the last two bytes. */
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I2C_CTL0(cfg->reg) |= I2C_CTL0_STOP;
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for (counter = 2U; counter > 0; counter--) {
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data->xfer_len--;
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i2c_gd32_xfer_read(data, cfg);
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}
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k_sem_give(&data->sync_sem);
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break;
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case 3:
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/* Clear ACKEN bit */
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I2C_CTL0(cfg->reg) &= ~I2C_CTL0_ACKEN;
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data->xfer_len--;
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i2c_gd32_xfer_read(data, cfg);
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break;
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default:
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i2c_gd32_handle_rbne(dev);
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break;
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}
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} else {
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i2c_gd32_handle_tbe(dev);
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}
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}
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static void i2c_gd32_handle_addsend(const struct device *dev)
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{
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struct i2c_gd32_data *data = dev->data;
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const struct i2c_gd32_config *cfg = dev->config;
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if ((data->current->flags & I2C_MSG_READ) && (data->xfer_len <= 2U)) {
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I2C_CTL0(cfg->reg) &= ~I2C_CTL0_ACKEN;
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}
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/* Clear ADDSEND bit */
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I2C_STAT0(cfg->reg);
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I2C_STAT1(cfg->reg);
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if (data->is_restart) {
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data->is_restart = false;
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data->current->flags &= ~I2C_MSG_RW_MASK;
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data->current->flags |= I2C_MSG_READ;
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/* Enter repeated start condition */
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I2C_CTL0(cfg->reg) |= I2C_CTL0_START;
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return;
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}
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if ((data->current->flags & I2C_MSG_READ) && (data->xfer_len == 1U)) {
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/* Enter stop condition */
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I2C_CTL0(cfg->reg) |= I2C_CTL0_STOP;
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}
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}
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static void i2c_gd32_event_isr(const struct device *dev)
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{
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struct i2c_gd32_data *data = dev->data;
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const struct i2c_gd32_config *cfg = dev->config;
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uint32_t stat;
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stat = I2C_STAT0(cfg->reg);
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if (stat & I2C_STAT0_SBSEND) {
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if (data->current->flags & I2C_MSG_READ) {
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I2C_DATA(cfg->reg) = (data->addr1 << 1U) | 1U;
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} else {
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I2C_DATA(cfg->reg) = (data->addr1 << 1U) | 0U;
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}
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} else if (stat & I2C_STAT0_ADD10SEND) {
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I2C_DATA(cfg->reg) = data->addr2;
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} else if (stat & I2C_STAT0_ADDSEND) {
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i2c_gd32_handle_addsend(dev);
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/*
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* Must handle BTC first.
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* For I2C_STAT0, BTC is the superset of RBNE and TBE.
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*/
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} else if (stat & I2C_STAT0_BTC) {
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i2c_gd32_handle_btc(dev);
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} else if (stat & I2C_STAT0_RBNE) {
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i2c_gd32_handle_rbne(dev);
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} else if (stat & I2C_STAT0_TBE) {
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i2c_gd32_handle_tbe(dev);
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}
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}
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static void i2c_gd32_error_isr(const struct device *dev)
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{
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struct i2c_gd32_data *data = dev->data;
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const struct i2c_gd32_config *cfg = dev->config;
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uint32_t stat;
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stat = I2C_STAT0(cfg->reg);
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if (stat & I2C_STAT0_BERR) {
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I2C_STAT0(cfg->reg) &= ~I2C_STAT0_BERR;
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data->errs |= I2C_GD32_ERR_BERR;
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}
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if (stat & I2C_STAT0_LOSTARB) {
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I2C_STAT0(cfg->reg) &= ~I2C_STAT0_LOSTARB;
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data->errs |= I2C_GD32_ERR_LARB;
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}
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if (stat & I2C_STAT0_AERR) {
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I2C_STAT0(cfg->reg) &= ~I2C_STAT0_AERR;
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data->errs |= I2C_GD32_ERR_AERR;
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}
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if (data->errs != 0U) {
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/* Enter stop condition */
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I2C_CTL0(cfg->reg) |= I2C_CTL0_STOP;
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k_sem_give(&data->sync_sem);
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}
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}
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static void i2c_gd32_log_err(struct i2c_gd32_data *data)
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{
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if (data->errs & I2C_GD32_ERR_BERR) {
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LOG_ERR("Bus error");
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}
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if (data->errs & I2C_GD32_ERR_LARB) {
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LOG_ERR("Arbitration lost");
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}
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if (data->errs & I2C_GD32_ERR_AERR) {
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LOG_ERR("No ACK received");
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}
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if (data->errs & I2C_GD32_ERR_BUSY) {
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LOG_ERR("I2C bus busy");
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}
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}
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static void i2c_gd32_xfer_begin(const struct device *dev)
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{
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struct i2c_gd32_data *data = dev->data;
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const struct i2c_gd32_config *cfg = dev->config;
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k_sem_reset(&data->sync_sem);
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data->errs = 0U;
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data->is_restart = false;
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/* Default to set ACKEN bit. */
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I2C_CTL0(cfg->reg) |= I2C_CTL0_ACKEN;
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if (data->current->flags & I2C_MSG_READ) {
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/* For 2 bytes read, use POAP bit to give NACK for the last data receiving. */
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if (data->xfer_len == 2U) {
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I2C_CTL0(cfg->reg) |= I2C_CTL0_POAP;
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}
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/*
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* For read on 10 bits address mode, start condition will happen twice.
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* Transfer sequence as below:
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* S addr1+W addr2 S addr1+R
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* Use a is_restart flag to cover this case.
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*/
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if (data->dev_config & I2C_ADDR_10_BITS) {
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data->is_restart = true;
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data->current->flags &= ~I2C_MSG_RW_MASK;
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}
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}
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i2c_gd32_enable_interrupts(cfg);
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/* Enter repeated start condition */
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I2C_CTL0(cfg->reg) |= I2C_CTL0_START;
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}
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static int i2c_gd32_xfer_end(const struct device *dev)
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{
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struct i2c_gd32_data *data = dev->data;
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const struct i2c_gd32_config *cfg = dev->config;
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i2c_gd32_disable_interrupts(cfg);
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/* Wait for stop condition is done. */
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while (I2C_STAT1(cfg->reg) & I2C_STAT1_I2CBSY) {
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/* NOP */
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}
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if (data->errs) {
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return -EIO;
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}
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return 0;
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}
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static int i2c_gd32_msg_read(const struct device *dev)
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{
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struct i2c_gd32_data *data = dev->data;
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const struct i2c_gd32_config *cfg = dev->config;
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if (I2C_STAT1(cfg->reg) & I2C_STAT1_I2CBSY) {
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data->errs = I2C_GD32_ERR_BUSY;
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return -EBUSY;
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}
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i2c_gd32_xfer_begin(dev);
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k_sem_take(&data->sync_sem, K_FOREVER);
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return i2c_gd32_xfer_end(dev);
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}
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static int i2c_gd32_msg_write(const struct device *dev)
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{
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struct i2c_gd32_data *data = dev->data;
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const struct i2c_gd32_config *cfg = dev->config;
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if (I2C_STAT1(cfg->reg) & I2C_STAT1_I2CBSY) {
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data->errs = I2C_GD32_ERR_BUSY;
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return -EBUSY;
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}
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i2c_gd32_xfer_begin(dev);
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k_sem_take(&data->sync_sem, K_FOREVER);
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return i2c_gd32_xfer_end(dev);
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}
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static int i2c_gd32_transfer(const struct device *dev,
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struct i2c_msg *msgs,
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uint8_t num_msgs,
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uint16_t addr)
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{
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struct i2c_gd32_data *data = dev->data;
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const struct i2c_gd32_config *cfg = dev->config;
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struct i2c_msg *current, *next;
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uint8_t itr;
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int err = 0;
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current = msgs;
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/* First message flags implicitly contain I2C_MSG_RESTART flag. */
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current->flags |= I2C_MSG_RESTART;
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for (uint8_t i = 1; i <= num_msgs; i++) {
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if (i < num_msgs) {
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next = current + 1;
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/*
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* If there have a R/W transfer state change between messages,
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* An explicit I2C_MSG_RESTART flag is needed for the second message.
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*/
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if ((current->flags & I2C_MSG_RW_MASK) !=
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(next->flags & I2C_MSG_RW_MASK)) {
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if ((next->flags & I2C_MSG_RESTART) == 0U) {
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return -EINVAL;
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}
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}
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/* Only the last message need I2C_MSG_STOP flag to free the Bus. */
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if (current->flags & I2C_MSG_STOP) {
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return -EINVAL;
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}
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} else {
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/* Last message flags implicitly contain I2C_MSG_STOP flag. */
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current->flags |= I2C_MSG_STOP;
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}
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if ((current->buf == NULL) ||
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(current->len == 0U)) {
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return -EINVAL;
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}
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current++;
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}
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k_sem_take(&data->bus_mutex, K_FOREVER);
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/* Enable i2c device */
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I2C_CTL0(cfg->reg) |= I2C_CTL0_I2CEN;
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if (data->dev_config & I2C_ADDR_10_BITS) {
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data->addr1 = 0xF0 | ((addr & BITS(8, 9)) >> 8U);
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data->addr2 = addr & BITS(0, 7);
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} else {
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data->addr1 = addr & BITS(0, 6);
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}
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for (uint8_t i = 0; i < num_msgs; i = itr) {
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data->current = &msgs[i];
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data->xfer_len = msgs[i].len;
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for (itr = i + 1; itr < num_msgs; itr++) {
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if ((data->current->flags & I2C_MSG_RW_MASK) !=
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(msgs[itr].flags & I2C_MSG_RW_MASK)) {
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break;
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}
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data->xfer_len += msgs[itr].len;
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}
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if (data->current->flags & I2C_MSG_READ) {
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err = i2c_gd32_msg_read(dev);
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} else {
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err = i2c_gd32_msg_write(dev);
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}
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if (err < 0) {
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i2c_gd32_log_err(data);
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break;
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}
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}
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/* Disable I2C device */
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I2C_CTL0(cfg->reg) &= ~I2C_CTL0_I2CEN;
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k_sem_give(&data->bus_mutex);
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return err;
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}
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static int i2c_gd32_configure(const struct device *dev,
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uint32_t dev_config)
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{
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struct i2c_gd32_data *data = dev->data;
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const struct i2c_gd32_config *cfg = dev->config;
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uint32_t pclk1, freq, clkc;
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int err = 0;
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k_sem_take(&data->bus_mutex, K_FOREVER);
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/* Disable I2C device */
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I2C_CTL0(cfg->reg) &= ~I2C_CTL0_I2CEN;
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/* GD32 i2c interface always connect to APB1. */
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pclk1 = rcu_clock_freq_get(CK_APB1);
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/* i2c clock frequency, us */
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freq = pclk1 / 1000000U;
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if (freq > I2CCLK_MAX) {
|
|
LOG_ERR("I2C max clock freq %u, current is %u\n",
|
|
I2CCLK_MAX, freq);
|
|
err = -ENOTSUP;
|
|
goto error;
|
|
}
|
|
|
|
/*
|
|
* Refer from SoC user manual.
|
|
* In standard mode:
|
|
* T_high = CLKC * T_pclk1
|
|
* T_low = CLKC * T_pclk1
|
|
*
|
|
* In fast mode and fast mode plus with DTCY=1:
|
|
* T_high = 9 * CLKC * T_pclk1
|
|
* T_low = 16 * CLKC * T_pclk1
|
|
*
|
|
* T_pclk1 is reciprocal of pclk1:
|
|
* T_pclk1 = 1 / pclk1
|
|
*
|
|
* T_high and T_low construct the bit transfer:
|
|
* T_high + T_low = 1 / bitrate
|
|
*
|
|
* And then, we can get the CLKC equation.
|
|
* Standard mode:
|
|
* CLKC = pclk1 / (bitrate * 2)
|
|
* Fast mode and fast mode plus:
|
|
* CLKC = pclk1 / (bitrate * 25)
|
|
*
|
|
* Variable list:
|
|
* T_high: high period of the SCL clock
|
|
* T_low: low period of the SCL clock
|
|
* T_pclk1: duration of single pclk1 pulse
|
|
* pclk1: i2c device clock frequency
|
|
* bitrate: 100 Kbits for standard mode
|
|
*/
|
|
switch (I2C_SPEED_GET(dev_config)) {
|
|
case I2C_SPEED_STANDARD:
|
|
if (freq < I2CCLK_MIN) {
|
|
LOG_ERR("I2C standard-mode min clock freq %u, current is %u\n",
|
|
I2CCLK_MIN, freq);
|
|
err = -ENOTSUP;
|
|
goto error;
|
|
}
|
|
I2C_CTL1(cfg->reg) &= ~I2C_CTL1_I2CCLK;
|
|
I2C_CTL1(cfg->reg) |= freq;
|
|
|
|
/* Standard-mode risetime maximum value: 1000ns */
|
|
if (freq == I2CCLK_MAX) {
|
|
I2C_RT(cfg->reg) = I2CCLK_MAX;
|
|
} else {
|
|
I2C_RT(cfg->reg) = freq + 1U;
|
|
}
|
|
|
|
/* CLKC = pclk1 / (bitrate * 2) */
|
|
clkc = pclk1 / (I2C_BITRATE_STANDARD * 2U);
|
|
|
|
I2C_CKCFG(cfg->reg) &= ~I2C_CKCFG_CLKC;
|
|
I2C_CKCFG(cfg->reg) |= clkc;
|
|
/* standard-mode */
|
|
I2C_CKCFG(cfg->reg) &= ~I2C_CKCFG_FAST;
|
|
|
|
break;
|
|
case I2C_SPEED_FAST:
|
|
if (freq < I2CCLK_FM_MIN) {
|
|
LOG_ERR("I2C fast-mode min clock freq %u, current is %u\n",
|
|
I2CCLK_FM_MIN, freq);
|
|
err = -ENOTSUP;
|
|
goto error;
|
|
}
|
|
|
|
/* Fast-mode risetime maximum value: 300ns */
|
|
I2C_RT(cfg->reg) = freq * 300U / 1000U + 1U;
|
|
|
|
/* CLKC = pclk1 / (bitrate * 25) */
|
|
clkc = pclk1 / (I2C_BITRATE_FAST * 25U);
|
|
if (clkc == 0U) {
|
|
clkc = 1U;
|
|
}
|
|
|
|
/* Default DCTY to 1 */
|
|
I2C_CKCFG(cfg->reg) |= I2C_CKCFG_DTCY;
|
|
I2C_CKCFG(cfg->reg) &= ~I2C_CKCFG_CLKC;
|
|
I2C_CKCFG(cfg->reg) |= clkc;
|
|
/* Transfer mode: fast-mode */
|
|
I2C_CKCFG(cfg->reg) |= I2C_CKCFG_FAST;
|
|
|
|
#ifdef I2C_FMPCFG
|
|
/* Disable transfer mode: fast-mode plus */
|
|
I2C_FMPCFG(cfg->reg) &= ~I2C_FMPCFG_FMPEN;
|
|
#endif /* I2C_FMPCFG */
|
|
|
|
break;
|
|
#ifdef I2C_FMPCFG
|
|
case I2C_SPEED_FAST_PLUS:
|
|
if (freq < I2CCLK_FM_PLUS_MIN) {
|
|
LOG_ERR("I2C fast-mode plus min clock freq %u, current is %u\n",
|
|
I2CCLK_FM_PLUS_MIN, freq);
|
|
err = -ENOTSUP;
|
|
goto error;
|
|
}
|
|
|
|
/* Fast-mode plus risetime maximum value: 120ns */
|
|
I2C_RT(cfg->reg) = freq * 120U / 1000U + 1U;
|
|
|
|
/* CLKC = pclk1 / (bitrate * 25) */
|
|
clkc = pclk1 / (I2C_BITRATE_FAST_PLUS * 25U);
|
|
if (clkc == 0U) {
|
|
clkc = 1U;
|
|
}
|
|
|
|
/* Default DCTY to 1 */
|
|
I2C_CKCFG(cfg->reg) |= I2C_CKCFG_DTCY;
|
|
I2C_CKCFG(cfg->reg) &= ~I2C_CKCFG_CLKC;
|
|
I2C_CKCFG(cfg->reg) |= clkc;
|
|
/* Transfer mode: fast-mode */
|
|
I2C_CKCFG(cfg->reg) |= I2C_CKCFG_FAST;
|
|
|
|
/* Enable transfer mode: fast-mode plus */
|
|
I2C_FMPCFG(cfg->reg) |= I2C_FMPCFG_FMPEN;
|
|
|
|
break;
|
|
#endif /* I2C_FMPCFG */
|
|
default:
|
|
err = -EINVAL;
|
|
goto error;
|
|
}
|
|
|
|
data->dev_config = dev_config;
|
|
error:
|
|
k_sem_give(&data->bus_mutex);
|
|
|
|
return err;
|
|
}
|
|
|
|
static struct i2c_driver_api i2c_gd32_driver_api = {
|
|
.configure = i2c_gd32_configure,
|
|
.transfer = i2c_gd32_transfer,
|
|
};
|
|
|
|
static int i2c_gd32_init(const struct device *dev)
|
|
{
|
|
struct i2c_gd32_data *data = dev->data;
|
|
const struct i2c_gd32_config *cfg = dev->config;
|
|
uint32_t bitrate_cfg;
|
|
int err;
|
|
|
|
err = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
|
|
if (err < 0) {
|
|
return err;
|
|
}
|
|
|
|
/* Mutex semaphore to protect the i2c api in multi-thread env. */
|
|
k_sem_init(&data->bus_mutex, 1, 1);
|
|
|
|
/* Sync semaphore to sync i2c state between isr and transfer api. */
|
|
k_sem_init(&data->sync_sem, 0, K_SEM_MAX_LIMIT);
|
|
|
|
rcu_periph_clock_enable(cfg->rcu_periph_clock);
|
|
|
|
cfg->irq_cfg_func();
|
|
|
|
bitrate_cfg = i2c_map_dt_bitrate(cfg->bitrate);
|
|
|
|
i2c_gd32_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#define I2C_GD32_INIT(inst) \
|
|
PINCTRL_DT_INST_DEFINE(inst); \
|
|
static void i2c_gd32_irq_cfg_func_##inst(void) \
|
|
{ \
|
|
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, event, irq), \
|
|
DT_INST_IRQ_BY_NAME(inst, event, priority), \
|
|
i2c_gd32_event_isr, \
|
|
DEVICE_DT_INST_GET(inst), \
|
|
0); \
|
|
irq_enable(DT_INST_IRQ_BY_NAME(inst, event, irq)); \
|
|
\
|
|
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, error, irq), \
|
|
DT_INST_IRQ_BY_NAME(inst, error, priority), \
|
|
i2c_gd32_error_isr, \
|
|
DEVICE_DT_INST_GET(inst), \
|
|
0); \
|
|
irq_enable(DT_INST_IRQ_BY_NAME(inst, error, irq)); \
|
|
} \
|
|
static struct i2c_gd32_data i2c_gd32_data_##inst; \
|
|
const static struct i2c_gd32_config i2c_gd32_cfg_##inst = { \
|
|
.reg = DT_INST_REG_ADDR(inst), \
|
|
.bitrate = DT_INST_PROP(inst, clock_frequency), \
|
|
.rcu_periph_clock = DT_INST_PROP(inst, rcu_periph_clock), \
|
|
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
|
|
.irq_cfg_func = i2c_gd32_irq_cfg_func_##inst, \
|
|
}; \
|
|
I2C_DEVICE_DT_INST_DEFINE(inst, \
|
|
i2c_gd32_init, NULL, \
|
|
&i2c_gd32_data_##inst, &i2c_gd32_cfg_##inst, \
|
|
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
|
|
&i2c_gd32_driver_api); \
|
|
|
|
DT_INST_FOREACH_STATUS_OKAY(I2C_GD32_INIT)
|