323 lines
8.0 KiB
C
323 lines
8.0 KiB
C
/*
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* Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT xlnx_xps_gpio_1_00_a
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#include <zephyr/device.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/sys/sys_io.h>
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#include "gpio_utils.h"
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/* AXI GPIO v2 register offsets (See Xilinx PG144 for details) */
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#define GPIO_DATA_OFFSET 0x0000
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#define GPIO_TRI_OFFSET 0x0004
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#define GPIO2_DATA_OFFSET 0x0008
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#define GPIO2_TRI_OFFSET 0x000c
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#define GIER_OFFSET 0x011c
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#define IPISR_OFFSET 0x0120
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#define IPIER_OFFSET 0x0128
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/* GIER bit definitions */
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#define GIER_GIE BIT(31)
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/* IPISR and IPIER bit definitions */
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#define IPIXX_CH1_IE BIT(0)
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#define IPIXX_CH2_IE BIT(1)
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/* Maximum number of GPIOs supported per channel */
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#define MAX_GPIOS 32
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struct gpio_xlnx_axi_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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mm_reg_t base;
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bool all_inputs : 1;
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bool all_outputs : 1;
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};
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struct gpio_xlnx_axi_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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/* Shadow registers for data out and tristate */
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uint32_t dout;
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uint32_t tri;
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};
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static inline uint32_t gpio_xlnx_axi_read_data(const struct device *dev)
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{
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const struct gpio_xlnx_axi_config *config = dev->config;
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return sys_read32(config->base + GPIO_DATA_OFFSET);
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}
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static inline void gpio_xlnx_axi_write_data(const struct device *dev,
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uint32_t val)
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{
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const struct gpio_xlnx_axi_config *config = dev->config;
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sys_write32(val, config->base + GPIO_DATA_OFFSET);
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}
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static inline void gpio_xlnx_axi_write_tri(const struct device *dev,
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uint32_t val)
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{
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const struct gpio_xlnx_axi_config *config = dev->config;
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sys_write32(val, config->base + GPIO_TRI_OFFSET);
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}
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static int gpio_xlnx_axi_pin_configure(const struct device *dev,
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gpio_pin_t pin,
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gpio_flags_t flags)
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{
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const struct gpio_xlnx_axi_config *config = dev->config;
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struct gpio_xlnx_axi_data *data = dev->data;
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unsigned int key;
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if (!(BIT(pin) & config->common.port_pin_mask)) {
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return -EINVAL;
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}
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if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
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return -ENOTSUP;
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}
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if ((flags & GPIO_SINGLE_ENDED) != 0) {
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return -ENOTSUP;
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}
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if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
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return -ENOTSUP;
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}
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if (((flags & GPIO_INPUT) != 0) && config->all_outputs) {
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return -ENOTSUP;
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}
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if (((flags & GPIO_OUTPUT) != 0) && config->all_inputs) {
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return -ENOTSUP;
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}
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key = irq_lock();
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switch (flags & GPIO_DIR_MASK) {
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case GPIO_INPUT:
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data->tri |= BIT(pin);
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break;
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case GPIO_OUTPUT:
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if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
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data->dout |= BIT(pin);
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} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
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data->dout &= ~BIT(pin);
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}
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data->tri &= ~BIT(pin);
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break;
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default:
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return -ENOTSUP;
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}
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gpio_xlnx_axi_write_data(dev, data->dout);
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gpio_xlnx_axi_write_tri(dev, data->tri);
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irq_unlock(key);
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return 0;
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}
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static int gpio_xlnx_axi_port_get_raw(const struct device *dev,
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gpio_port_value_t *value)
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{
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*value = gpio_xlnx_axi_read_data(dev);
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return 0;
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}
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static int gpio_xlnx_axi_port_set_masked_raw(const struct device *dev,
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gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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struct gpio_xlnx_axi_data *data = dev->data;
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unsigned int key;
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key = irq_lock();
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data->dout = (data->dout & ~mask) | (mask & value);
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gpio_xlnx_axi_write_data(dev, data->dout);
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irq_unlock(key);
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return 0;
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}
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static int gpio_xlnx_axi_port_set_bits_raw(const struct device *dev,
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gpio_port_pins_t pins)
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{
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struct gpio_xlnx_axi_data *data = dev->data;
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unsigned int key;
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key = irq_lock();
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data->dout |= pins;
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gpio_xlnx_axi_write_data(dev, data->dout);
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irq_unlock(key);
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return 0;
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}
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static int gpio_xlnx_axi_port_clear_bits_raw(const struct device *dev,
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gpio_port_pins_t pins)
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{
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struct gpio_xlnx_axi_data *data = dev->data;
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unsigned int key;
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key = irq_lock();
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data->dout &= ~pins;
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gpio_xlnx_axi_write_data(dev, data->dout);
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irq_unlock(key);
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return 0;
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}
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static int gpio_xlnx_axi_port_toggle_bits(const struct device *dev,
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gpio_port_pins_t pins)
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{
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struct gpio_xlnx_axi_data *data = dev->data;
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unsigned int key;
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key = irq_lock();
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data->dout ^= pins;
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gpio_xlnx_axi_write_data(dev, data->dout);
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irq_unlock(key);
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return 0;
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}
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static int gpio_xlnx_axi_pin_interrupt_configure(const struct device *dev,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(pin);
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ARG_UNUSED(mode);
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ARG_UNUSED(trig);
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/*
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* The Xilinx AXI GPIO IP only supports a port-wide pin change
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* interrupt. This does not map well to the current Zephyr GPIO IRQ API.
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*/
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return -ENOTSUP;
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}
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static int gpio_xlnx_axi_manage_callback(const struct device *dev,
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struct gpio_callback *cb,
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bool set)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(cb);
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ARG_UNUSED(set);
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return -ENOTSUP;
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}
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static uint32_t gpio_xlnx_axi_get_pending_int(const struct device *dev)
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{
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return 0;
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}
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static int gpio_xlnx_axi_init(const struct device *dev)
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{
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struct gpio_xlnx_axi_data *data = dev->data;
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gpio_xlnx_axi_write_data(dev, data->dout);
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gpio_xlnx_axi_write_tri(dev, data->tri);
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return 0;
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}
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static const struct gpio_driver_api gpio_xlnx_axi_driver_api = {
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.pin_configure = gpio_xlnx_axi_pin_configure,
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.port_get_raw = gpio_xlnx_axi_port_get_raw,
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.port_set_masked_raw = gpio_xlnx_axi_port_set_masked_raw,
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.port_set_bits_raw = gpio_xlnx_axi_port_set_bits_raw,
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.port_clear_bits_raw = gpio_xlnx_axi_port_clear_bits_raw,
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.port_toggle_bits = gpio_xlnx_axi_port_toggle_bits,
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.pin_interrupt_configure = gpio_xlnx_axi_pin_interrupt_configure,
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.manage_callback = gpio_xlnx_axi_manage_callback,
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.get_pending_int = gpio_xlnx_axi_get_pending_int,
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};
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#define GPIO_XLNX_AXI_GPIO2_HAS_COMPAT_STATUS_OKAY(n) \
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UTIL_AND( \
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DT_NODE_HAS_COMPAT(DT_CHILD(DT_DRV_INST(n), gpio2), \
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xlnx_xps_gpio_1_00_a_gpio2), \
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DT_NODE_HAS_STATUS(DT_CHILD(DT_DRV_INST(n), gpio2), \
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okay) \
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)
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#define GPIO_XLNX_AXI_GPIO2_COND_INIT(n) \
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IF_ENABLED(UTIL_AND( \
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DT_INST_PROP_OR(n, xlnx_is_dual, 1), \
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GPIO_XLNX_AXI_GPIO2_HAS_COMPAT_STATUS_OKAY(n) \
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), \
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(GPIO_XLNX_AXI_GPIO2_INIT(n)));
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#define GPIO_XLNX_AXI_GPIO2_INIT(n) \
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static struct gpio_xlnx_axi_data gpio_xlnx_axi_##n##_2_data = { \
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.dout = DT_INST_PROP_OR(n, xlnx_dout_default_2, 0), \
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.tri = DT_INST_PROP_OR(n, xlnx_tri_default_2, \
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GENMASK(MAX_GPIOS - 1, 0)), \
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}; \
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\
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static const struct gpio_xlnx_axi_config \
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gpio_xlnx_axi_##n##_2_config = { \
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.common = { \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(\
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DT_INST_PROP_OR(n, xlnx_gpio2_width, \
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MAX_GPIOS)), \
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}, \
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.base = DT_INST_REG_ADDR(n) + GPIO2_DATA_OFFSET, \
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.all_inputs = DT_INST_PROP_OR(n, xlnx_all_inputs2, 0), \
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.all_outputs = DT_INST_PROP_OR(n, xlnx_all_outputs2, 0),\
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}; \
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\
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DEVICE_DT_DEFINE(DT_CHILD(DT_DRV_INST(n), gpio2), \
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&gpio_xlnx_axi_init, \
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NULL, \
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&gpio_xlnx_axi_##n##_2_data, \
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&gpio_xlnx_axi_##n##_2_config, \
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PRE_KERNEL_1, \
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CONFIG_GPIO_INIT_PRIORITY, \
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&gpio_xlnx_axi_driver_api);
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#define GPIO_XLNX_AXI_INIT(n) \
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static struct gpio_xlnx_axi_data gpio_xlnx_axi_##n##_data = { \
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.dout = DT_INST_PROP_OR(n, xlnx_dout_default, 0), \
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.tri = DT_INST_PROP_OR(n, xlnx_tri_default, \
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GENMASK(MAX_GPIOS - 1, 0)), \
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}; \
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\
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static const struct gpio_xlnx_axi_config \
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gpio_xlnx_axi_##n##_config = { \
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.common = { \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(\
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DT_INST_PROP_OR(n, xlnx_gpio_width, \
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MAX_GPIOS)), \
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}, \
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.base = DT_INST_REG_ADDR(n), \
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.all_inputs = DT_INST_PROP_OR(n, xlnx_all_inputs, 0), \
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.all_outputs = DT_INST_PROP_OR(n, xlnx_all_outputs, 0), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, \
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&gpio_xlnx_axi_init, \
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NULL, \
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&gpio_xlnx_axi_##n##_data, \
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&gpio_xlnx_axi_##n##_config, \
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PRE_KERNEL_1, \
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CONFIG_GPIO_INIT_PRIORITY, \
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&gpio_xlnx_axi_driver_api); \
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GPIO_XLNX_AXI_GPIO2_COND_INIT(n);
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DT_INST_FOREACH_STATUS_OKAY(GPIO_XLNX_AXI_INIT)
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