182 lines
4.1 KiB
Plaintext
182 lines
4.1 KiB
Plaintext
/*
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* Copyright (c) 2021 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <xtensa/xtensa.dtsi>
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#include <mem.h>
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#include <zephyr/dt-bindings/clock/imx_ccm.h>
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#include <zephyr/dt-bindings/dai/esai.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx6";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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clic: interrupt-controller@0 {
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compatible = "cdns,xtensa-core-intc";
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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};
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};
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irqsteer: interrupt-controller@510a0000 {
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compatible = "nxp,irqsteer-intc";
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reg = <0x510a0000 DT_SIZE_K(64)>;
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#size-cells = <0>;
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#address-cells = <1>;
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master0: interrupt-controller@0 {
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compatible = "nxp,irqsteer-master";
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 19 0 0>;
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};
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master1: interrupt-controller@1 {
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compatible = "nxp,irqsteer-master";
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reg = <1>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 20 0 0>;
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};
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master2: interrupt-controller@2 {
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compatible = "nxp,irqsteer-master";
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reg = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 21 0 0>;
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};
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master3: interrupt-controller@3 {
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compatible = "nxp,irqsteer-master";
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reg = <3>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 22 0 0>;
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};
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master4: interrupt-controller@4 {
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compatible = "nxp,irqsteer-master";
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reg = <4>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 23 0 0>;
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};
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master5: interrupt-controller@5 {
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compatible = "nxp,irqsteer-master";
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reg = <5>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 24 0 0>;
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};
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master6: interrupt-controller@6 {
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compatible = "nxp,irqsteer-master";
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reg = <6>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 25 0 0>;
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};
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master7: interrupt-controller@7 {
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compatible = "nxp,irqsteer-master";
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reg = <7>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts-extended = <&clic 26 0 0>;
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};
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};
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sram0: memory@92400000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x92400000 DT_SIZE_K(512)>;
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};
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sram1: memory@92c00000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x92c00000 DT_SIZE_K(512)>;
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};
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edma0: dma@591f0000 {
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compatible = "nxp,edma";
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reg = <0x591f0000 (DT_SIZE_K(64) * 33)>;
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valid-channels = <6>, <7>, <14>, <15>;
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interrupts-extended = <&master6 58>, <&master6 58>,
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<&master5 29>, <&master5 29>;
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#dma-cells = <2>;
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status = "disabled";
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};
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sai1: dai@59050000 {
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compatible = "nxp,dai-sai";
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reg = <0x59050000 DT_SIZE_K(64)>;
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interrupt-parent = <&master5>;
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interrupts = <28>;
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dai-index = <1>;
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dmas = <&edma0 15 0>, <&edma0 14 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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esai0: dai@59010000 {
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compatible = "nxp,dai-esai";
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reg = <0x59010000 DT_SIZE_K(64)>;
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dmas = <&edma0 7 0>, <&edma0 6 0>;
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dma-names = "tx", "rx";
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esai-pin-modes = <ESAI_PIN_HCKR ESAI_PIN_DISCONNECTED>,
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<ESAI_PIN_HCKT ESAI_PIN_DISCONNECTED>,
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<ESAI_PIN_SDO4_SDI1 ESAI_PIN_DISCONNECTED>,
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<ESAI_PIN_SDO3_SDI2 ESAI_PIN_DISCONNECTED>,
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<ESAI_PIN_SDO2_SDI3 ESAI_PIN_DISCONNECTED>,
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<ESAI_PIN_SDO1 ESAI_PIN_DISCONNECTED>;
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status = "disabled";
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};
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/* LSIO MU2, used to interact with the SCFW */
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scu_mu: mailbox@5d1d0000 {
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reg = <0x5d1d0000 DT_SIZE_K(64)>;
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};
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scu: system-controller {
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ccm: clock-controller {
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compatible = "nxp,imx-ccm";
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#clock-cells = <3>;
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};
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iomuxc: iomuxc {
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compatible = "nxp,imx-iomuxc-scu";
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pinctrl: pinctrl {
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compatible = "nxp,imx8-pinctrl";
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};
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};
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};
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lpuart2: serial@5a080000 {
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compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart";
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reg = <0x5a080000 DT_SIZE_K(4)>;
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interrupt-parent = <&master4>;
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interrupts = <3>;
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/* this is actually LPUART2 clock but the macro indexing starts at 1 */
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clocks = <&ccm IMX_CCM_LPUART3_CLK 0x0 0x0>;
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status = "disabled";
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};
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};
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