438fe6dbba
Having the lowest possible interrupt priority is causing the tests\arch\arm\arm_irq_zero_latency_levels test to fail. This test reserves 2 priority levels for the low latency interrupts. Since CYW20829 supports 3 interrupt bits, 6 becomes an invalid value when 2 levels are reserved for the low latency interrupts. Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com> |
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| .. | ||
| arc/synopsys | ||
| arm | ||
| arm64 | ||
| bindings | ||
| common | ||
| nios2/intel | ||
| posix | ||
| riscv | ||
| sparc/gaisler | ||
| x86/intel | ||
| xtensa | ||
| Kconfig | ||
| binding-template.yaml | ||