zephyr/soc/riscv32/riscv-privilege
Anas Nashif c2c6a6a245 qemu_riscv32: use hifive1 configuration
Use hifive1 configuration for this qemu and set
SYS_CLOCK_HW_CYCLES_PER_SEC to 10000000

Fixes #10043

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-11-05 11:00:38 -05:00
..
common qemu_riscv32: use hifive1 configuration 2018-11-05 11:00:38 -05:00
miv drivers: serial: uart_miv: Convert to use DTS 2018-11-03 06:58:23 -04:00
sifive-freedom DT: Rename from dts.fixup to dts_fixup.h 2018-10-08 11:38:56 -04:00
CMakeLists.txt
Kconfig
Kconfig.defconfig
Kconfig.soc