zephyr/boards/riscv
Jose Manuel Pacheco Luna 8e5e812252 boards: rv32m1_vega: Documentation and sanity test support
Edited the index.rst file to say spi functionality is included. Also
edited the .yaml file in the boards directory to support spi for sanity
tests.

Signed-off-by: Jose Manuel Pacheco Luna <manuel.pacheco@nxp.com>
2019-12-20 17:06:10 +01:00
..
hifive1 boards: hifive1*: fix ticks per second 2019-11-27 13:32:16 -05:00
hifive1_revb boards: hifive1*: fix ticks per second 2019-11-27 13:32:16 -05:00
litex_vexriscv boards: litex_vexriscv: Enable networking 2019-12-18 10:35:15 +02:00
m2gl025_miv boards: Clean up references to env variable PROJECT_SOURCE_DIR 2019-09-12 13:16:16 -05:00
qemu_riscv32 dts: jedec,spi-nor: require size property 2019-11-09 15:26:06 +01:00
qemu_riscv64 riscv: kconfig: Remove assignment to promptless CONFIG_64BIT symbol 2019-12-09 19:58:36 -06:00
rv32m1_vega boards: rv32m1_vega: Documentation and sanity test support 2019-12-20 17:06:10 +01:00
index.rst riscv32: rename to riscv 2019-08-02 13:54:48 -07:00