100 lines
3.6 KiB
C
100 lines
3.6 KiB
C
/*
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* Copyright (c) 2016-2017 Piotr Mienkowski
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* Copyright (c) 2021 ATL Electronics
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* SPDX-License-Identifier: Apache-2.0
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*/
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/** @file
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* @brief Cypress PSoC-6 MCU family General Purpose Input Output (GPIO)
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* module HAL driver.
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*/
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#ifndef _CYPRESS_PSOC6_SOC_GPIO_H_
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#define _CYPRESS_PSOC6_SOC_GPIO_H_
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#include <zephyr/types.h>
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#include <soc.h>
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/*
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* Pin flags/attributes
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*/
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#define SOC_GPIO_DEFAULT (0)
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#define SOC_GPIO_FLAGS_POS (0)
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#define SOC_GPIO_FLAGS_MASK (0x3F << SOC_GPIO_FLAGS_POS)
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#define SOC_GPIO_PULLUP_POS (0)
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#define SOC_GPIO_PULLUP (1 << SOC_GPIO_PULLUP_POS)
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#define SOC_GPIO_PULLDOWN_POS (1)
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#define SOC_GPIO_PULLDOWN (1 << SOC_GPIO_PULLDOWN_POS)
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#define SOC_GPIO_OPENDRAIN_POS (2)
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#define SOC_GPIO_OPENDRAIN (1 << SOC_GPIO_OPENDRAIN_POS)
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#define SOC_GPIO_OPENSOURCE_POS (3)
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#define SOC_GPIO_OPENSOURCE (1 << SOC_GPIO_OPENSOURCE_POS)
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/* Push-Pull means Strong, see dts/pinctrl/pincfg-node.yaml */
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#define SOC_GPIO_PUSHPULL_POS (4)
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#define SOC_GPIO_PUSHPULL (1 << SOC_GPIO_PUSHPULL_POS)
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/* Input-Enable means Input-Buffer, see dts/pinctrl/pincfg-node.yaml */
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#define SOC_GPIO_INPUTENABLE_POS (5)
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#define SOC_GPIO_INPUTENABLE (1 << SOC_GPIO_INPUTENABLE_POS)
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/* Bit field: SOC_GPIO_IN_FILTER */
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#define SOC_GPIO_IN_FILTER_POS (6)
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#define SOC_GPIO_IN_FILTER_MASK (3 << SOC_GPIO_IN_FILTER_POS)
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#define SOC_GPIO_IN_FILTER_NONE (0 << SOC_GPIO_IN_FILTER_POS)
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#define SOC_GPIO_IN_FILTER_DEBOUNCE (1 << SOC_GPIO_IN_FILTER_POS)
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#define SOC_GPIO_IN_FILTER_DEGLITCH (2 << SOC_GPIO_IN_FILTER_POS)
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#define SOC_GPIO_INT_ENABLE (1 << 8)
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/* Bit field: SOC_GPIO_INT_TRIG */
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#define SOC_GPIO_INT_TRIG_POS (9)
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#define SOC_GPIO_INT_TRIG_MASK (3 << SOC_GPIO_INT_TRIG_POS)
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/** Interrupt is triggered by a level detection event. */
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#define SOC_GPIO_INT_TRIG_LEVEL (0 << SOC_GPIO_INT_TRIG_POS)
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/** Interrupt is triggered by an edge detection event. */
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#define SOC_GPIO_INT_TRIG_EDGE (1 << SOC_GPIO_INT_TRIG_POS)
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/** Interrupt is triggered by any edge detection event. */
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#define SOC_GPIO_INT_TRIG_DOUBLE_EDGE (2 << SOC_GPIO_INT_TRIG_POS)
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/** Interrupt is triggered by a high level / rising edge detection event */
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#define SOC_GPIO_INT_ACTIVE_HIGH (1 << 11)
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/* Bit field: SOC_GPIO_FUNC */
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#define SOC_GPIO_FUNC_POS (16)
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#define SOC_GPIO_FUNC_MASK (0x1F << SOC_GPIO_FUNC_POS)
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struct soc_gpio_pin {
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GPIO_PRT_Type *regs; /** pointer to registers of the GPIO controller */
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uint32_t pinum; /** pin number */
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uint32_t flags; /** pin flags/attributes */
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};
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/**
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* @brief Configure GPIO pin(s).
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*
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* Configure one or several pins belonging to the same GPIO port.
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* Example scenarios:
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* - configure pin(s) as input with debounce filter enabled.
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* - connect pin(s) to a HSIOM function and enable pull-up.
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* - configure pin(s) as open drain output.
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* All pins are configured in the same way.
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*
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* @param pin pin's configuration data such as pin mask, pin attributes, etc.
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*/
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void soc_gpio_configure(const struct soc_gpio_pin *pin);
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/**
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* @brief Configure a list of GPIO pin(s).
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*
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* Configure an arbitrary amount of pins in an arbitrary way. Each
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* configuration entry is a single item in an array passed as an
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* argument to the function.
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*
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* @param pins an array where each item contains pin's configuration data.
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* @param size size of the pin list.
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*/
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void soc_gpio_list_configure(const struct soc_gpio_pin pins[], size_t size);
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#endif /* _CYPRESS_PSOC6_SOC_GPIO_H_ */
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