Carlo Caione 3e92f11d1f riscv: Optimize t* registers usage ... In preparation for the support of RV32E optimize a bit the t* registers usage limiting that to t{0-2}. Signed-off-by: Carlo Caione <ccaione@baylibre.com>		2022-06-05 14:44:06 +02:00
..
arc	ARC: define PROPERTY_OUTPUT_FORMAT for all ARC elf formats	2022-05-10 14:12:25 -04:00
arm	arch: arm: Add support for multiple zero-latency irq priorities	2022-05-13 08:38:28 -05:00
arm64	arm64: smp: Fix the wrong secondary core stack size	2022-05-17 11:45:16 +09:00
common	arch: gen_isr_tables: migrate to <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
mips	asm: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
nios2	asm: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
posix	include: add more missing zephyr/ prefixes	2022-05-27 15:20:27 -07:00
riscv	riscv: Optimize t* registers usage	2022-06-05 14:44:06 +02:00
sparc	asm: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
x86	asm: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
xtensa	include: add zephyr/ on script generated #include	2022-05-27 15:20:27 -07:00
CMakeLists.txt	cmake: fix include directories to work with out-of-tree arch	2020-08-05 08:06:07 -04:00
Kconfig	kconfig: Add CONFIG_DCACHE option	2022-05-24 08:47:20 -07:00