230 lines
5.5 KiB
C
230 lines
5.5 KiB
C
/*
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* Copyright (c) 2013-2015, Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file
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* @brief Board configuration macros for the Quark X1000 SoC
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*
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* This header file is used to specify and describe SoC-level aspects for
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* the Quark X1000 SoC.
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*/
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#ifndef __SOC_H_
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#define __SOC_H_
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#include <misc/util.h>
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#ifndef _ASMLANGUAGE
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#include <device.h>
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#include <drivers/rand32.h>
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#endif
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#ifdef CONFIG_IOAPIC
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#include <drivers/ioapic.h>
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#endif
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/*
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* Ethernet (DesignWare)
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*/
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#define ETH_DW_PCI_VENDOR_ID 0x8086
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#define ETH_DW_PCI_DEVICE_ID 0x0937
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#define ETH_DW_PCI_CLASS 0x02
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#define ETH_DW_0_BASE_ADDR 0x90002000
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#define ETH_DW_0_IRQ 18
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#define ETH_DW_0_PCI_BUS 0
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#define ETH_DW_0_PCI_DEV 20
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#define ETH_DW_0_PCI_FUNCTION 6
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#define ETH_DW_0_PCI_BAR 0
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/*
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* SPI
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*/
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#define SPI_INTEL_VENDOR_ID 0x8086
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#define SPI_INTEL_DEVICE_ID 0x935
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#define SPI_INTEL_CLASS 0x0C
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#define SPI_INTEL_PORT_0_REGS 0x90009000
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#define SPI_INTEL_PORT_0_IRQ 16
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#define SPI_INTEL_PORT_0_BUS 0
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#define SPI_INTEL_PORT_0_DEV 21
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#define SPI_INTEL_PORT_0_FUNCTION 0
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#define SPI_INTEL_PORT_1_REGS 0x90008000
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#define SPI_INTEL_PORT_1_IRQ 17
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#define SPI_INTEL_PORT_1_BUS 0
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#define SPI_INTEL_PORT_1_DEV 21
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#define SPI_INTEL_PORT_1_FUNCTION 1
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#define SPI_INTEL_IRQ_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH)
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/*
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* GPIO
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*/
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#define GPIO_SCH_LEGACY_IO_PORTS_ACCESS
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#define GPIO_SCH_0_BASE_ADDR 0x1080
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#define GPIO_SCH_0_BITS 2
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#define GPIO_SCH_1_BASE_ADDR 0x10A0
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#define GPIO_SCH_1_BITS 6
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#define GPIO_DW_PCI_VENDOR_ID 0x8086
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#define GPIO_DW_PCI_DEVICE_ID 0x0934
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#define GPIO_DW_PCI_CLASS 0x0C
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#define GPIO_DW_0_BASE_ADDR 0x90006000
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#define GPIO_DW_0_IRQ 18
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#define GPIO_DW_0_BITS 8
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#define GPIO_DW_0_PCI_BUS 0
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#define GPIO_DW_0_PCI_DEV 21
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#define GPIO_DW_0_PCI_FUNCTION 2
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#define GPIO_DW_0_PCI_BAR 1
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#if defined(CONFIG_IOAPIC)
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#define GPIO_DW_0_IRQ_FLAGS (IOAPIC_LEVEL | IOAPIC_LOW)
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#endif
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/*
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* I2C
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*/
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#define I2C_DW_PCI_VENDOR_ID 0x8086
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#define I2C_DW_PCI_DEVICE_ID 0x0934
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#define I2C_DW_PCI_CLASS 0x0C
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#define I2C_DW_0_BASE_ADDR 0x90007000
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#define I2C_DW_0_IRQ 18
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#define I2C_DW_0_PCI_BUS 0
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#define I2C_DW_0_PCI_DEV 21
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#define I2C_DW_0_PCI_FUNCTION 2
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#define I2C_DW_0_PCI_BAR 0
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#if defined(CONFIG_IOAPIC)
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#define I2C_DW_IRQ_FLAGS (IOAPIC_LEVEL | IOAPIC_LOW)
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#endif
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/*
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* UART
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*/
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#define UART_NS16550_PORT_0_BASE_ADDR 0x9000f000
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#define UART_NS16550_PORT_0_IRQ 0
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#define UART_NS16550_PORT_0_CLK_FREQ 44236800
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#define UART_NS16550_PORT_0_PCI_CLASS 0x07
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#define UART_NS16550_PORT_0_PCI_BUS 0
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#define UART_NS16550_PORT_0_PCI_DEV 20
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#define UART_NS16550_PORT_0_PCI_VENDOR_ID 0x8086
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#define UART_NS16550_PORT_0_PCI_DEVICE_ID 0x0936
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#define UART_NS16550_PORT_0_PCI_FUNC 1
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#define UART_NS16550_PORT_0_PCI_BAR 0
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#define UART_NS16550_PORT_1_BASE_ADDR 0x9000b000
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#define UART_NS16550_PORT_1_IRQ 17
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#define UART_NS16550_PORT_1_CLK_FREQ 44236800
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#define UART_NS16550_PORT_1_PCI_CLASS 0x07
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#define UART_NS16550_PORT_1_PCI_BUS 0
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#define UART_NS16550_PORT_1_PCI_DEV 20
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#define UART_NS16550_PORT_1_PCI_VENDOR_ID 0x8086
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#define UART_NS16550_PORT_1_PCI_DEVICE_ID 0x0936
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#define UART_NS16550_PORT_1_PCI_FUNC 5
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#define UART_NS16550_PORT_1_PCI_BAR 0
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#ifdef CONFIG_IOAPIC
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#define UART_IRQ_FLAGS (IOAPIC_LEVEL | IOAPIC_LOW)
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#endif /* CONFIG_IOAPIC */
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define NUM_STD_IRQS 16 /* number of "standard" IRQs on an x86 platform */
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#define INT_VEC_IRQ0 0x20 /* Vector number for IRQ0 */
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/*
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* The IRQ_CONNECT() API connects to a (virtualized) IRQ and the
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* associated interrupt controller is programmed with the allocated vector.
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* The Quark board virtualizes IRQs as follows:
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*
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* - The first CONFIG_IOAPIC_NUM_RTES IRQs are provided by the IOAPIC
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* - The remaining IRQs are provided by the LOAPIC.
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*
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* Thus, for example, if the IOAPIC supports 24 IRQs:
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*
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* - IRQ0 to IRQ23 map to IOAPIC IRQ0 to IRQ23
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* - IRQ24 to IRQ29 map to LOAPIC LVT entries as follows:
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*
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* IRQ24 -> LOAPIC_TIMER
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* IRQ25 -> LOAPIC_THERMAL
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* IRQ26 -> LOAPIC_PMC
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* IRQ27 -> LOAPIC_LINT0
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* IRQ28 -> LOAPIC_LINT1
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* IRQ29 -> LOAPIC_ERROR
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*/
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/* PCI definitions */
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#define PCI_BUS_NUMBERS 2
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#define PCI_CTRL_ADDR_REG 0xCF8
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#define PCI_CTRL_DATA_REG 0xCFC
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#define PCI_INTA 1
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#define PCI_INTB 2
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#define PCI_INTC 3
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#define PCI_INTD 4
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/**
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*
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* @brief Convert PCI interrupt PIN to IRQ
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*
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* The routine uses "standard design consideration" and implies that
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* INTA (pin 1) -> IRQ 16
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* INTB (pin 2) -> IRQ 17
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* INTC (pin 3) -> IRQ 18
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* INTD (pin 4) -> IRQ 19
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*
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* In case a mini-PCIe card is used, the IRQs are swizzled:
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* INTA (pin 1) -> IRQ 17
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* INTB (pin 2) -> IRQ 18
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* INTC (pin 3) -> IRQ 19
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* INTD (pin 4) -> IRQ 16
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*
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* @return IRQ number, -1 if the result is incorrect
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*
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*/
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static inline int pci_pin2irq(int bus, int dev, int pin)
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{
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if (bus < 0 || bus > 1) {
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return -1;
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}
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if ((pin < PCI_INTA) || (pin > PCI_INTD)) {
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return -1;
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}
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return NUM_STD_IRQS + ((pin - 1 + bus) & 3);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* __SOC_H_ */
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