130 lines
3.4 KiB
C
130 lines
3.4 KiB
C
/* spi_intel.h - Intel's SPI driver private definitions */
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/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __SPI_INTEL_PRIV_H__
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#define __SPI_INTEL_PRIV_H__
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#ifdef CONFIG_PCI
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#include <pci/pci.h>
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#include <pci/pci_mgr.h>
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#endif /* CONFIG_PCI */
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef void (*spi_intel_config_t)(void);
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struct spi_intel_config {
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uint32_t irq;
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spi_intel_config_t config_func;
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#ifdef CONFIG_SPI_CS_GPIO
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char *cs_gpio_name;
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uint32_t cs_gpio_pin;
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#endif /* CONFIG_SPI_CS_GPIO */
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};
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struct spi_intel_data {
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uint32_t regs;
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#ifdef CONFIG_PCI
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struct pci_dev_info pci_dev;
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#endif /* CONFIG_PCI */
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struct k_sem device_sync_sem;
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uint8_t error;
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uint8_t padding[3];
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#ifdef CONFIG_SPI_CS_GPIO
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struct device *cs_gpio_port;
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#endif /* CONFIG_SPI_CS_GPIO */
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uint32_t sscr0;
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uint32_t sscr1;
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const uint8_t *tx_buf;
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uint8_t *rx_buf;
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uint32_t t_buf_len;
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uint32_t r_buf_len;
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uint32_t transmitted;
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uint32_t received;
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uint32_t trans_len;
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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uint32_t device_power_state;
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#endif
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};
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/* Registers */
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#define INTEL_SPI_REG_SSCR0 (0x00)
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#define INTEL_SPI_REG_SSCR1 (0x04)
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#define INTEL_SPI_REG_SSSR (0x08)
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#define INTEL_SPI_REG_SSDR (0x10)
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#define INTEL_SPI_REG_DDS_RATE (0x28)
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#define INTEL_SPI_CLK_DIV_MASK (0x000000ff)
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#define INTEL_SPI_DDS_RATE_MASK (0xffffff00)
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/* SSCR0 settings */
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#define INTEL_SPI_SSCR0_DSS(__bpw) ((__bpw) - 1)
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#define INTEL_SPI_SSCR0_SSE (0x1 << 7)
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#define INTEL_SPI_SSCR0_SSE_BIT (7)
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#define INTEL_SPI_SSCR0_SCR(__msf) \
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((__msf & INTEL_SPI_CLK_DIV_MASK) << 8)
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/* SSCR1 settings */
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#define INTEL_SPI_SSCR1_TIE_BIT (1)
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#define INTEL_SPI_SSCR1_RIE (0x1)
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#define INTEL_SPI_SSCR1_TIE (0x1 << 1)
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#define INTEL_SPI_SSCR1_LBM (0x1 << 2)
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#define INTEL_SPI_SSCR1_SPO (0x1 << 3)
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#define INTEL_SPI_SSCR1_SPH (0x1 << 4)
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#define INTEL_SPI_SSCR1_TFT_MASK (0x1f << 6)
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#define INTEL_SPI_SSCR1_TFT(__tft) \
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(((__tft) - 1) << 6)
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#define INTEL_SPI_SSCR1_RFT_MASK (0x1f << 11)
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#define INTEL_SPI_SSCR1_RFT(__rft) \
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(((__rft) - 1) << 11)
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#define INTEL_SPI_SSCR1_EFWR (0x1 << 16)
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#define INTEL_SPI_SSCR1_STRF (0x1 << 17)
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#define INTEL_SPI_SSCR1_TFT_DFLT (8)
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#define INTEL_SPI_SSCR1_RFT_DFLT (1)
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/* SSSR settings */
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#define INTEL_SPI_SSSR_TNF (0x4)
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#define INTEL_SPI_SSSR_RNE (0x8)
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#define INTEL_SPI_SSSR_TFS (0x20)
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#define INTEL_SPI_SSSR_RFS (0x40)
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#define INTEL_SPI_SSSR_ROR (0x80)
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#define INTEL_SPI_SSSR_TFL_MASK (0x1f << 8)
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#define INTEL_SPI_SSSR_TFL_EMPTY (0x00)
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#define INTEL_SPI_SSSR_RFL_MASK (0x1f << 13)
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#define INTEL_SPI_SSSR_RFL_EMPTY (0x1f)
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#define INTEL_SPI_SSSR_TFL(__status) \
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((__status & INTEL_SPI_SSSR_TFL_MASK) >> 8)
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#define INTEL_SPI_SSSR_RFL(__status) \
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((__status & INTEL_SPI_SSSR_RFL_MASK) >> 13)
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#define INTEL_SPI_SSSR_BSY_BIT (4)
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#define INTEL_SPI_SSSR_ROR_BIT (7)
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/* DSS_RATE settings */
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#define INTEL_SPI_DSS_RATE(__msf) \
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((__msf & (INTEL_SPI_DDS_RATE_MASK)) >> 8)
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#ifdef __cplusplus
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}
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#endif
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#endif /* __SPI_INTEL_PRIV_H__ */
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