zephyr/boards/riscv32
Nathaniel Graff 7eb6bd6dfe boards/hifive1: Enable SPI driver
Enable the SPI driver on the HiFive 1

This makes the following configurations choices for the HiFive 1:

The SPI 0 peripheral driver is not enabled by default because it is in
charge of mapping the SPI flash into memory. This can be configured
using the CONFIG_SIFIVE_SPI_0_ROM KConfig option.

The SPI 1 peripheral driver is enabled by default and the pinmux is
configured for all of its outputs

The SPI 2 peripheral driver is enabled by default because it is present
in the DTS for the FE310, but because the QFN48 package used on the
HiFive 1 doesn't route those pins from the silicon die, the pinmux can't
enable the SPI 2 pins.

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-02-06 09:00:00 -06:00
..
hifive1 boards/hifive1: Enable SPI driver 2019-02-06 09:00:00 -06:00
m2gl025_miv sanitycheck: Enable Renode tests on m2gl025_miv 2019-01-14 09:12:07 -05:00
qemu_riscv32 shell: remove Console dependencies 2018-12-07 12:11:11 +01:00
rv32m1_vega boards: rv32m1_vega: fix the location of the YAML file 2019-01-30 13:42:03 -06:00
index.rst