446 lines
19 KiB
C
446 lines
19 KiB
C
/*
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* Copyright (c) Henrik Brix Andersen <henrik@brixandersen.dk>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_ARM_XILINX_ZYNQ7000_COMMON_PINCTRL_SOC_H_
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#define ZEPHYR_SOC_ARM_XILINX_ZYNQ7000_COMMON_PINCTRL_SOC_H_
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#include <zephyr/devicetree.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/types.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* MIO_PIN_xx SLCR register fields (from Xilinx UG585 v1.13, B.28 SLCR) */
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#define MIO_PIN_DISABLE_RCVR_MASK BIT(13)
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#define MIO_PIN_DISABLE_RCVR(val) FIELD_PREP(MIO_PIN_DISABLE_RCVR_MASK, val)
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#define MIO_PIN_PULLUP_MASK BIT(12)
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#define MIO_PIN_PULLUP(val) FIELD_PREP(MIO_PIN_PULLUP_MASK, val)
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#define MIO_PIN_IO_TYPE_MASK GENMASK(11, 9)
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#define MIO_PIN_IO_TYPE(val) FIELD_PREP(MIO_PIN_IO_TYPE_MASK, val)
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#define MIO_PIN_SPEED_MASK BIT(8)
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#define MIO_PIN_SPEED(val) FIELD_PREP(MIO_PIN_SPEED_MASK, val)
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#define MIO_PIN_L3_SEL_MASK GENMASK(7, 5)
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#define MIO_PIN_L3_SEL(val) FIELD_PREP(MIO_PIN_L3_SEL_MASK, val)
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#define MIO_PIN_L2_SEL_MASK GENMASK(4, 3)
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#define MIO_PIN_L2_SEL(val) FIELD_PREP(MIO_PIN_L2_SEL_MASK, val)
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#define MIO_PIN_L1_SEL_MASK BIT(2)
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#define MIO_PIN_L1_SEL(val) FIELD_PREP(MIO_PIN_L1_SEL_MASK, val)
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#define MIO_PIN_L0_SEL_MASK BIT(1)
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#define MIO_PIN_L0_SEL(val) FIELD_PREP(MIO_PIN_L0_SEL_MASK, val)
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#define MIO_PIN_TRI_ENABLE_MASK BIT(0)
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#define MIO_PIN_TRI_ENABLE(val) FIELD_PREP(MIO_PIN_TRI_ENABLE_MASK, val)
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/* MIO_PIN_xx SLCR register L3..L0 multiplexing fields combined */
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#define MIO_PIN_LX_SEL_MASK \
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(MIO_PIN_L3_SEL_MASK | MIO_PIN_L2_SEL_MASK | MIO_PIN_L1_SEL_MASK | MIO_PIN_L0_SEL_MASK)
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#define MIO_PIN_LX_SEL(l3, l2, l1, l0) \
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(MIO_PIN_L3_SEL(l3) | MIO_PIN_L2_SEL(l2) | MIO_PIN_L1_SEL(l1) | MIO_PIN_L0_SEL(l0))
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/* MIO pin function multiplexing (from Xilinx UG585 v1.13, B.28 SLCR) */
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#define MIO_PIN_FUNCTION_ETHERNET0 MIO_PIN_LX_SEL(0x0, 0x0, 0x0, 0x1)
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#define MIO_PIN_FUNCTION_ETHERNET1 MIO_PIN_LX_SEL(0x0, 0x0, 0x0, 0x1)
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#define MIO_PIN_FUNCTION_MDIO0 MIO_PIN_LX_SEL(0x4, 0x0, 0x0, 0x0)
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#define MIO_PIN_FUNCTION_MDIO1 MIO_PIN_LX_SEL(0x5, 0x0, 0x0, 0x0)
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#define MIO_PIN_FUNCTION_QSPI0 MIO_PIN_LX_SEL(0x0, 0x0, 0x0, 0x1)
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#define MIO_PIN_FUNCTION_QSPI1 MIO_PIN_LX_SEL(0x0, 0x0, 0x0, 0x1)
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#define MIO_PIN_FUNCTION_QSPI_FBCLK MIO_PIN_LX_SEL(0x0, 0x0, 0x0, 0x1)
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#define MIO_PIN_FUNCTION_QSPI_CS1 MIO_PIN_LX_SEL(0x0, 0x0, 0x0, 0x1)
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#define MIO_PIN_FUNCTION_SPI0 MIO_PIN_LX_SEL(0x5, 0x0, 0x0, 0x0)
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#define MIO_PIN_FUNCTION_SPI0_SS MIO_PIN_LX_SEL(0x5, 0x0, 0x0, 0x0)
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#define MIO_PIN_FUNCTION_SPI1 MIO_PIN_LX_SEL(0x5, 0x0, 0x0, 0x0)
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#define MIO_PIN_FUNCTION_SPI1_SS MIO_PIN_LX_SEL(0x5, 0x0, 0x0, 0x0)
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#define MIO_PIN_FUNCTION_SDIO0 MIO_PIN_LX_SEL(0x4, 0x0, 0x0, 0x0)
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#define MIO_PIN_FUNCTION_SDIO0_PC MIO_PIN_LX_SEL(0x0, 0x3, 0x0, 0x0)
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#define MIO_PIN_FUNCTION_SDIO1 MIO_PIN_LX_SEL(0x4, 0x0, 0x0, 0x0)
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#define MIO_PIN_FUNCTION_SDIO1_PC MIO_PIN_LX_SEL(0x0, 0x3, 0x0, 0x0)
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#define MIO_PIN_FUNCTION_SMC0_NOR MIO_PIN_LX_SEL(0x0, 0x1, 0x0, 0x0)
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#define MIO_PIN_FUNCTION_SMC0_NOR_CS1 MIO_PIN_LX_SEL(0x0, 0x2, 0x0, 0x0)
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#define MIO_PIN_FUNCTION_SMC0_NOR_ADDR25 MIO_PIN_LX_SEL(0x0, 0x1, 0x0, 0x0)
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#define MIO_PIN_FUNCTION_SMC0_NAND MIO_PIN_LX_SEL(0x0, 0x2, 0x0, 0x0)
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#define MIO_PIN_FUNCTION_CAN0 MIO_PIN_LX_SEL(0x1, 0x0, 0x0, 0x0)
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#define MIO_PIN_FUNCTION_CAN1 MIO_PIN_LX_SEL(0x1, 0x0, 0x0, 0x0)
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#define MIO_PIN_FUNCTION_UART0 MIO_PIN_LX_SEL(0x7, 0x0, 0x0, 0x0)
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#define MIO_PIN_FUNCTION_UART1 MIO_PIN_LX_SEL(0x7, 0x0, 0x0, 0x0)
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#define MIO_PIN_FUNCTION_I2C0 MIO_PIN_LX_SEL(0x2, 0x0, 0x0, 0x0)
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#define MIO_PIN_FUNCTION_I2C1 MIO_PIN_LX_SEL(0x2, 0x0, 0x0, 0x0)
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#define MIO_PIN_FUNCTION_TTC0 MIO_PIN_LX_SEL(0x6, 0x0, 0x0, 0x0)
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#define MIO_PIN_FUNCTION_TTC1 MIO_PIN_LX_SEL(0x6, 0x0, 0x0, 0x0)
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#define MIO_PIN_FUNCTION_SWDT0 MIO_PIN_LX_SEL(0x3, 0x0, 0x0, 0x0)
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#define MIO_PIN_FUNCTION_GPIO0 MIO_PIN_LX_SEL(0x0, 0x0, 0x0, 0x0)
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#define MIO_PIN_FUNCTION_USB0 MIO_PIN_LX_SEL(0x0, 0x0, 0x1, 0x0)
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#define MIO_PIN_FUNCTION_USB1 MIO_PIN_LX_SEL(0x0, 0x0, 0x1, 0x0)
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/* MIO SDIO CD/WP pin selection (from Xilinx UG585 v1.13, B.28 SLCR) */
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#define MIO_PIN_SPECIAL_FUNCTION_SDIO0_CD 1
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#define MIO_PIN_SPECIAL_OFFSET_SDIO0_CD 0x0130
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#define MIO_PIN_SPECIAL_MASK_SDIO0_CD GENMASK(21, 16)
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#define MIO_PIN_SPECIAL_SHIFT_SDIO0_CD 16
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#define MIO_PIN_SPECIAL_FUNCTION_SDIO0_WP 1
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#define MIO_PIN_SPECIAL_OFFSET_SDIO0_WP 0x0130
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#define MIO_PIN_SPECIAL_MASK_SDIO0_WP GENMASK(5, 0)
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#define MIO_PIN_SPECIAL_SHIFT_SDIO0_WP 0
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#define MIO_PIN_SPECIAL_FUNCTION_SDIO1_CD 1
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#define MIO_PIN_SPECIAL_OFFSET_SDIO1_CD 0x0134
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#define MIO_PIN_SPECIAL_MASK_SDIO1_CD GENMASK(21, 16)
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#define MIO_PIN_SPECIAL_SHIFT_SDIO1_CD 16
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#define MIO_PIN_SPECIAL_FUNCTION_SDIO1_WP 1
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#define MIO_PIN_SPECIAL_OFFSET_SDIO1_WP 0x0134
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#define MIO_PIN_SPECIAL_MASK_SDIO1_WP GENMASK(5, 0)
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#define MIO_PIN_SPECIAL_SHIFT_SDIO1_WP 0
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/* MIO pin numbers */
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#define MIO0 0
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#define MIO1 1
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#define MIO2 2
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#define MIO3 3
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#define MIO4 4
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#define MIO5 5
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#define MIO6 6
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#define MIO7 7
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#define MIO8 8
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#define MIO9 9
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#define MIO10 10
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#define MIO11 11
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#define MIO12 12
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#define MIO13 13
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#define MIO14 14
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#define MIO15 15
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#define MIO16 16
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#define MIO17 17
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#define MIO18 18
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#define MIO19 19
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#define MIO20 20
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#define MIO21 21
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#define MIO22 22
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#define MIO23 23
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#define MIO24 24
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#define MIO25 25
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#define MIO26 26
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#define MIO27 27
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#define MIO28 28
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#define MIO29 29
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#define MIO30 30
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#define MIO31 31
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#define MIO32 32
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#define MIO33 33
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#define MIO34 34
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#define MIO35 35
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#define MIO36 36
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#define MIO37 37
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#define MIO38 38
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#define MIO39 39
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#define MIO40 40
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#define MIO41 41
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#define MIO42 42
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#define MIO43 43
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#define MIO44 44
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#define MIO45 45
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#define MIO46 46
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#define MIO47 47
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#define MIO48 48
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#define MIO49 49
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#define MIO50 50
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#define MIO51 51
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#define MIO52 52
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#define MIO53 53
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/* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
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#define MIO_GROUP_ETHERNET0_0_GRP_PINS 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27
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#define MIO_GROUP_ETHERNET1_0_GRP_PINS 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
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#define MIO_GROUP_MDIO0_0_GRP_PINS 52, 53
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#define MIO_GROUP_MDIO1_0_GRP_PINS 52, 53
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#define MIO_GROUP_QSPI0_0_GRP_PINS 1, 2, 3, 4, 5, 6
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#define MIO_GROUP_QSPI1_0_GRP_PINS 9, 10, 11, 12, 13
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#define MIO_GROUP_QSPI_FBCLK_PINS 8
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#define MIO_GROUP_QSPI_CS1_GRP_PINS 0
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#define MIO_GROUP_SPI0_0_GRP_PINS 16, 17, 21
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#define MIO_GROUP_SPI0_0_SS0_PINS 18
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#define MIO_GROUP_SPI0_0_SS1_PINS 19
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#define MIO_GROUP_SPI0_0_SS2_PINS 20
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#define MIO_GROUP_SPI0_1_GRP_PINS 28, 29, 33
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#define MIO_GROUP_SPI0_1_SS0_PINS 30
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#define MIO_GROUP_SPI0_1_SS1_PINS 31
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#define MIO_GROUP_SPI0_1_SS2_PINS 32
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#define MIO_GROUP_SPI0_2_GRP_PINS 40, 41, 45
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#define MIO_GROUP_SPI0_2_SS0_PINS 42
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#define MIO_GROUP_SPI0_2_SS1_PINS 43
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#define MIO_GROUP_SPI0_2_SS2_PINS 44
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#define MIO_GROUP_SPI1_0_GRP_PINS 10, 11, 12
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#define MIO_GROUP_SPI1_0_SS0_PINS 13
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#define MIO_GROUP_SPI1_0_SS1_PINS 14
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#define MIO_GROUP_SPI1_0_SS2_PINS 15
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#define MIO_GROUP_SPI1_1_GRP_PINS 22, 23, 24
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#define MIO_GROUP_SPI1_1_SS0_PINS 25
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#define MIO_GROUP_SPI1_1_SS1_PINS 26
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#define MIO_GROUP_SPI1_1_SS2_PINS 27
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#define MIO_GROUP_SPI1_2_GRP_PINS 34, 35, 36
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#define MIO_GROUP_SPI1_2_SS0_PINS 37
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#define MIO_GROUP_SPI1_2_SS1_PINS 38
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#define MIO_GROUP_SPI1_2_SS2_PINS 39
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#define MIO_GROUP_SPI1_3_GRP_PINS 46, 47, 48
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#define MIO_GROUP_SPI1_3_SS0_PINS 49
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#define MIO_GROUP_SPI1_3_SS1_PINS 50
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#define MIO_GROUP_SPI1_3_SS2_PINS 51
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#define MIO_GROUP_SDIO0_0_GRP_PINS 16, 17, 18, 19, 20, 21
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#define MIO_GROUP_SDIO0_1_GRP_PINS 28, 29, 30, 31, 32, 33
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#define MIO_GROUP_SDIO0_2_GRP_PINS 40, 41, 42, 43, 44, 45
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#define MIO_GROUP_SDIO1_0_GRP_PINS 10, 11, 12, 13, 14, 15
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#define MIO_GROUP_SDIO1_1_GRP_PINS 22, 23, 24, 25, 26, 27
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#define MIO_GROUP_SDIO1_2_GRP_PINS 34, 35, 36, 37, 38, 39
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#define MIO_GROUP_SDIO1_3_GRP_PINS 46, 47, 48, 49, 50, 51
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#define MIO_GROUP_SDIO0_EMIO_WP_PINS 54
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#define MIO_GROUP_SDIO0_EMIO_CD_PINS 55
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#define MIO_GROUP_SDIO1_EMIO_WP_PINS 56
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#define MIO_GROUP_SDIO1_EMIO_CD_PINS 57
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#define MIO_GROUP_SMC0_NOR_PINS 0, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, \
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16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \
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28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
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#define MIO_GROUP_SMC0_NOR_CS1_GRP_PINS 1
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#define MIO_GROUP_SMC0_NOR_ADDR25_GRP_PINS 1
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#define MIO_GROUP_SMC0_NAND_PINS 0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, \
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12, 13, 14, 16, 17, 18, 19, 20, 21, 22, 23
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#define MIO_GROUP_CAN0_0_GRP_PINS 10, 11
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#define MIO_GROUP_CAN0_1_GRP_PINS 14, 15
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#define MIO_GROUP_CAN0_2_GRP_PINS 18, 19
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#define MIO_GROUP_CAN0_3_GRP_PINS 22, 23
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#define MIO_GROUP_CAN0_4_GRP_PINS 26, 27
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#define MIO_GROUP_CAN0_5_GRP_PINS 30, 31
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#define MIO_GROUP_CAN0_6_GRP_PINS 34, 35
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#define MIO_GROUP_CAN0_7_GRP_PINS 38, 39
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#define MIO_GROUP_CAN0_8_GRP_PINS 42, 43
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#define MIO_GROUP_CAN0_9_GRP_PINS 46, 47
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#define MIO_GROUP_CAN0_10_GRP_PINS 50, 51
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#define MIO_GROUP_CAN1_0_GRP_PINS 8, 9
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#define MIO_GROUP_CAN1_1_GRP_PINS 12, 13
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#define MIO_GROUP_CAN1_2_GRP_PINS 16, 17
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#define MIO_GROUP_CAN1_3_GRP_PINS 20, 21
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#define MIO_GROUP_CAN1_4_GRP_PINS 24, 25
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#define MIO_GROUP_CAN1_5_GRP_PINS 28, 29
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#define MIO_GROUP_CAN1_6_GRP_PINS 32, 33
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#define MIO_GROUP_CAN1_7_GRP_PINS 36, 37
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#define MIO_GROUP_CAN1_8_GRP_PINS 40, 41
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#define MIO_GROUP_CAN1_9_GRP_PINS 44, 45
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#define MIO_GROUP_CAN1_10_GRP_PINS 48, 49
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#define MIO_GROUP_CAN1_11_GRP_PINS 52, 53
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#define MIO_GROUP_UART0_0_GRP_PINS 10, 11
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#define MIO_GROUP_UART0_1_GRP_PINS 14, 15
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#define MIO_GROUP_UART0_2_GRP_PINS 18, 19
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#define MIO_GROUP_UART0_3_GRP_PINS 22, 23
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#define MIO_GROUP_UART0_4_GRP_PINS 26, 27
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#define MIO_GROUP_UART0_5_GRP_PINS 30, 31
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#define MIO_GROUP_UART0_6_GRP_PINS 34, 35
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#define MIO_GROUP_UART0_7_GRP_PINS 38, 39
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#define MIO_GROUP_UART0_8_GRP_PINS 42, 43
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#define MIO_GROUP_UART0_9_GRP_PINS 46, 47
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#define MIO_GROUP_UART0_10_GRP_PINS 50, 51
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#define MIO_GROUP_UART1_0_GRP_PINS 8, 9
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#define MIO_GROUP_UART1_1_GRP_PINS 12, 13
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#define MIO_GROUP_UART1_2_GRP_PINS 16, 17
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#define MIO_GROUP_UART1_3_GRP_PINS 20, 21
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#define MIO_GROUP_UART1_4_GRP_PINS 24, 25
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#define MIO_GROUP_UART1_5_GRP_PINS 28, 29
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#define MIO_GROUP_UART1_6_GRP_PINS 32, 33
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#define MIO_GROUP_UART1_7_GRP_PINS 36, 37
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#define MIO_GROUP_UART1_8_GRP_PINS 40, 41
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#define MIO_GROUP_UART1_9_GRP_PINS 44, 45
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#define MIO_GROUP_UART1_10_GRP_PINS 48, 49
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#define MIO_GROUP_UART1_11_GRP_PINS 52, 53
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#define MIO_GROUP_I2C0_0_GRP_PINS 10, 11
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#define MIO_GROUP_I2C0_1_GRP_PINS 14, 15
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#define MIO_GROUP_I2C0_2_GRP_PINS 18, 19
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#define MIO_GROUP_I2C0_3_GRP_PINS 22, 23
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#define MIO_GROUP_I2C0_4_GRP_PINS 26, 27
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#define MIO_GROUP_I2C0_5_GRP_PINS 30, 31
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#define MIO_GROUP_I2C0_6_GRP_PINS 34, 35
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#define MIO_GROUP_I2C0_7_GRP_PINS 38, 39
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#define MIO_GROUP_I2C0_8_GRP_PINS 42, 43
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#define MIO_GROUP_I2C0_9_GRP_PINS 46, 47
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#define MIO_GROUP_I2C0_10_GRP_PINS 50, 51
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#define MIO_GROUP_I2C1_0_GRP_PINS 12, 13
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#define MIO_GROUP_I2C1_1_GRP_PINS 16, 17
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#define MIO_GROUP_I2C1_2_GRP_PINS 20, 21
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#define MIO_GROUP_I2C1_3_GRP_PINS 24, 25
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#define MIO_GROUP_I2C1_4_GRP_PINS 28, 29
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#define MIO_GROUP_I2C1_5_GRP_PINS 32, 33
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#define MIO_GROUP_I2C1_6_GRP_PINS 36, 37
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#define MIO_GROUP_I2C1_7_GRP_PINS 40, 41
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#define MIO_GROUP_I2C1_8_GRP_PINS 44, 45
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#define MIO_GROUP_I2C1_9_GRP_PINS 48, 49
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#define MIO_GROUP_I2C1_10_GRP_PINS 52, 53
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#define MIO_GROUP_TTC0_0_GRP_PINS 18, 19
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#define MIO_GROUP_TTC0_1_GRP_PINS 30, 31
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#define MIO_GROUP_TTC0_2_GRP_PINS 42, 43
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#define MIO_GROUP_TTC1_0_GRP_PINS 16, 17
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#define MIO_GROUP_TTC1_1_GRP_PINS 28, 29
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#define MIO_GROUP_TTC1_2_GRP_PINS 40, 41
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#define MIO_GROUP_SWDT0_0_GRP_PINS 14, 15
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#define MIO_GROUP_SWDT0_1_GRP_PINS 26, 27
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#define MIO_GROUP_SWDT0_2_GRP_PINS 38, 39
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#define MIO_GROUP_SWDT0_3_GRP_PINS 50, 51
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#define MIO_GROUP_SWDT0_4_GRP_PINS 52, 53
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#define MIO_GROUP_GPIO0_0_GRP_PINS 0
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#define MIO_GROUP_GPIO0_1_GRP_PINS 1
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#define MIO_GROUP_GPIO0_2_GRP_PINS 2
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#define MIO_GROUP_GPIO0_3_GRP_PINS 3
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#define MIO_GROUP_GPIO0_4_GRP_PINS 4
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#define MIO_GROUP_GPIO0_5_GRP_PINS 5
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#define MIO_GROUP_GPIO0_6_GRP_PINS 6
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#define MIO_GROUP_GPIO0_7_GRP_PINS 7
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#define MIO_GROUP_GPIO0_8_GRP_PINS 8
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#define MIO_GROUP_GPIO0_9_GRP_PINS 9
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#define MIO_GROUP_GPIO0_10_GRP_PINS 10
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#define MIO_GROUP_GPIO0_11_GRP_PINS 11
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#define MIO_GROUP_GPIO0_12_GRP_PINS 12
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#define MIO_GROUP_GPIO0_13_GRP_PINS 13
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#define MIO_GROUP_GPIO0_14_GRP_PINS 14
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#define MIO_GROUP_GPIO0_15_GRP_PINS 15
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#define MIO_GROUP_GPIO0_16_GRP_PINS 16
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#define MIO_GROUP_GPIO0_17_GRP_PINS 17
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#define MIO_GROUP_GPIO0_18_GRP_PINS 18
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#define MIO_GROUP_GPIO0_19_GRP_PINS 19
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#define MIO_GROUP_GPIO0_20_GRP_PINS 20
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#define MIO_GROUP_GPIO0_21_GRP_PINS 21
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#define MIO_GROUP_GPIO0_22_GRP_PINS 22
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#define MIO_GROUP_GPIO0_23_GRP_PINS 23
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#define MIO_GROUP_GPIO0_24_GRP_PINS 24
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#define MIO_GROUP_GPIO0_25_GRP_PINS 25
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#define MIO_GROUP_GPIO0_26_GRP_PINS 26
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#define MIO_GROUP_GPIO0_27_GRP_PINS 27
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#define MIO_GROUP_GPIO0_28_GRP_PINS 28
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#define MIO_GROUP_GPIO0_29_GRP_PINS 29
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#define MIO_GROUP_GPIO0_30_GRP_PINS 30
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#define MIO_GROUP_GPIO0_31_GRP_PINS 31
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#define MIO_GROUP_GPIO0_32_GRP_PINS 32
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#define MIO_GROUP_GPIO0_33_GRP_PINS 33
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#define MIO_GROUP_GPIO0_34_GRP_PINS 34
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#define MIO_GROUP_GPIO0_35_GRP_PINS 35
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#define MIO_GROUP_GPIO0_36_GRP_PINS 36
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#define MIO_GROUP_GPIO0_37_GRP_PINS 37
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#define MIO_GROUP_GPIO0_38_GRP_PINS 38
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#define MIO_GROUP_GPIO0_39_GRP_PINS 39
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#define MIO_GROUP_GPIO0_40_GRP_PINS 40
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#define MIO_GROUP_GPIO0_41_GRP_PINS 41
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#define MIO_GROUP_GPIO0_42_GRP_PINS 42
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#define MIO_GROUP_GPIO0_43_GRP_PINS 43
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#define MIO_GROUP_GPIO0_44_GRP_PINS 44
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#define MIO_GROUP_GPIO0_45_GRP_PINS 45
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#define MIO_GROUP_GPIO0_46_GRP_PINS 46
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#define MIO_GROUP_GPIO0_47_GRP_PINS 47
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#define MIO_GROUP_GPIO0_48_GRP_PINS 48
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#define MIO_GROUP_GPIO0_49_GRP_PINS 49
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#define MIO_GROUP_GPIO0_50_GRP_PINS 50
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#define MIO_GROUP_GPIO0_51_GRP_PINS 51
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#define MIO_GROUP_GPIO0_52_GRP_PINS 52
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#define MIO_GROUP_GPIO0_53_GRP_PINS 53
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#define MIO_GROUP_USB0_0_GRP_PINS 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
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#define MIO_GROUP_USB1_0_GRP_PINS 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51
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typedef struct {
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uint32_t mask;
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uint32_t val;
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uint16_t offset;
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} pinctrl_soc_pin_t;
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/* Iterate over each pinctrl-n phandle child */
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#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
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{DT_FOREACH_CHILD(DT_PHANDLE(node_id, prop), \
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Z_PINCTRL_STATE_PIN_CHILD_INIT)};
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/*
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* If child has groups property:
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* - Iterate over each pin in group and populate pinctrl_soc_pin_t
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* If child has pins property:
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* - Iterate over each pin in pins and populate pinctrl_soc_pin_t
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*/
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#define Z_PINCTRL_STATE_PIN_CHILD_INIT(node_id) \
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COND_CODE_1(DT_NODE_HAS_PROP(node_id, groups), \
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(DT_FOREACH_PROP_ELEM(node_id, groups, Z_PINCTRL_STATE_PIN_CHILD_GROUP_INIT)), \
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()) \
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COND_CODE_1(DT_NODE_HAS_PROP(node_id, pins), \
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(DT_FOREACH_PROP_ELEM(node_id, pins, Z_PINCTRL_STATE_PIN_CHILD_PIN_INIT)), \
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())
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/* Process each pin in group using MIO_GROUP_x_PINS macros defined above */
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#define Z_PINCTRL_STATE_PIN_CHILD_GROUP_INIT(node_id, prop, idx) \
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FOR_EACH_FIXED_ARG(Z_PINCTRL_STATE_PIN_CHILD_GROUP_PIN_INIT, (), node_id, \
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UTIL_CAT(UTIL_CAT(MIO_GROUP_, \
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DT_STRING_UPPER_TOKEN_BY_IDX(node_id, prop, idx)), _PINS))
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/* Reverse order of arguments to adapt between FOR_EACH_FIXED_ARG() and DT_FOREACH_PROP_ELEM() */
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#define Z_PINCTRL_STATE_PIN_CHILD_GROUP_PIN_INIT(pin, node_id) \
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Z_PINCTRL_STATE_PIN_INIT(node_id, pin)
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/* Process pin using MIOx macros defines above */
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#define Z_PINCTRL_STATE_PIN_CHILD_PIN_INIT(node_id, prop, idx) \
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Z_PINCTRL_STATE_PIN_INIT(node_id, DT_STRING_UPPER_TOKEN_BY_IDX(node_id, prop, idx))
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/* Process pin functions and special functions (CD, WP) */
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#define Z_PINCTRL_STATE_PIN_INIT(node_id, pin) \
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COND_CODE_1(Z_PINCTRL_STATE_PIN_IS_SPECIAL_FUNCTION(node_id), \
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(Z_PINCTRL_STATE_PIN_SPECIAL_INIT(node_id, pin)), \
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(Z_PINCTRL_STATE_PIN_FUNCTION_INIT(node_id, pin)))
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/* Determine if pin has special function */
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#define Z_PINCTRL_STATE_PIN_IS_SPECIAL_FUNCTION(node_id) \
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COND_CODE_1(DT_NODE_HAS_PROP(node_id, function), \
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(UTIL_CAT(MIO_PIN_SPECIAL_FUNCTION_, DT_STRING_UPPER_TOKEN(node_id, function))), \
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(0))
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/* Populate pinctrl_soc_pin_t for each special function pin */
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#define Z_PINCTRL_STATE_PIN_SPECIAL_INIT(node_id, pin) \
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{ \
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.mask = UTIL_CAT(MIO_PIN_SPECIAL_MASK_, \
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DT_STRING_UPPER_TOKEN(node_id, function)), \
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.val = pin << UTIL_CAT(MIO_PIN_SPECIAL_SHIFT_, \
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DT_STRING_UPPER_TOKEN(node_id, function)), \
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.offset = UTIL_CAT(MIO_PIN_SPECIAL_OFFSET_, \
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DT_STRING_UPPER_TOKEN(node_id, function)), \
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},
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/* Populate pinctrl_soc_pin_t for each pin */
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#define Z_PINCTRL_STATE_PIN_FUNCTION_INIT(node_id, pin) \
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{ \
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.mask = Z_PINCTRL_STATE_PIN_MASK(node_id), \
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.val = Z_PINCTRL_STATE_PIN_VAL(node_id), \
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.offset = pin * sizeof(uint32_t), \
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},
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#define Z_PINCTRL_STATE_PIN_MASK(node_id) \
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COND_CODE_1(DT_NODE_HAS_PROP(node_id, function), (MIO_PIN_LX_SEL_MASK), (0U)) | \
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COND_CODE_1(DT_PROP(node_id, bias_disable), \
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(MIO_PIN_PULLUP_MASK | MIO_PIN_TRI_ENABLE_MASK), (0U)) | \
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COND_CODE_1(DT_PROP(node_id, low_power_disable), (MIO_PIN_DISABLE_RCVR_MASK), (0U)) | \
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COND_CODE_1(DT_NODE_HAS_PROP(node_id, power_source), (MIO_PIN_IO_TYPE_MASK), (0U)) | \
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COND_CODE_1(DT_NODE_HAS_PROP(node_id, slew_rate), (MIO_PIN_SPEED_MASK), (0U))
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#define Z_PINCTRL_STATE_PIN_VAL(node_id) \
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COND_CODE_1(DT_NODE_HAS_PROP(node_id, function), \
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(UTIL_CAT(MIO_PIN_FUNCTION_, DT_STRING_UPPER_TOKEN(node_id, function))), (0U)) | \
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MIO_PIN_TRI_ENABLE(DT_PROP(node_id, bias_high_impedance)) | \
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MIO_PIN_PULLUP(DT_PROP(node_id, bias_pull_up)) | \
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MIO_PIN_DISABLE_RCVR(DT_PROP(node_id, low_power_enable)) | \
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MIO_PIN_IO_TYPE(DT_PROP_OR(node_id, power_source, (0U))) | \
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MIO_PIN_SPEED(DT_PROP_OR(node_id, slew_rate, (0U)))
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_SOC_ARM_XILINX_ZYNQ7000_COMMON_PINCTRL_SOC_H_ */
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