213 lines
6.3 KiB
Plaintext
213 lines
6.3 KiB
Plaintext
# Nordic Semiconductor nRF53 MCU line
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# Copyright (c) 2019 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_NRF53X
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config SOC_NRF5340_CPUAPP
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select CPU_HAS_NRF_IDAU
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select CPU_HAS_FPU
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select ARMV8_M_DSP
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select HAS_POWEROFF
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select SOC_COMPATIBLE_NRF5340_CPUAPP
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imply SOC_NRF53_RTC_PRETICK
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imply SOC_NRF53_ANOMALY_168_WORKAROUND
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config SOC_NRF5340_CPUNET
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select ARM_ON_EXIT_CPU_IDLE
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select SOC_COMPATIBLE_NRF5340_CPUNET
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imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
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imply SOC_NRF53_RTC_PRETICK if !WDT_NRFX
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imply SOC_NRF53_ANOMALY_168_WORKAROUND
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config SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
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bool "Workaround for nRF5340 anomaly 160"
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imply SOC_NRF53_ANOMALY_160_WORKAROUND
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help
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Indicates that the workaround for the anomaly 160 that affects
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the nRF5340 SoC should be applied.
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This option is enabled by default for the Application MCU when
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DC/DC mode is enabled for the VREGMAIN or VREGRADIO regulator
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and always for the Network MCU.
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If this option is enabled, but the workaround cannot be applied,
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because the system clock is disabled, a related cmake warning is
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issued.
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config SOC_NRF53_ANOMALY_160_WORKAROUND
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bool
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depends on SYS_CLOCK_EXISTS
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select ARM_ON_ENTER_CPU_IDLE_HOOK
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config SOC_NRF53_ANOMALY_168_WORKAROUND
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bool "Workaround for nRF5340 anomaly 168"
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select ARM_ON_EXIT_CPU_IDLE
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help
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Indicates that the workaround for the anomaly 168 that affects
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the nRF5340 SoC should be applied.
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The workaround involves execution of 8 NOP instructions when the CPU
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exist its idle state (when the WFI/WFE instruction returns) and it is
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enabled by default for both the application and network core.
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config SOC_NRF53_ANOMALY_168_WORKAROUND_FOR_EXECUTION_FROM_RAM
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bool "Extend the workaround to execution at 128 MHz from RAM"
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depends on SOC_NRF53_ANOMALY_168_WORKAROUND && SOC_NRF5340_CPUAPP
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help
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Indicates that the anomaly 168 workaround is to be extended to cover
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also a specific case when the WFI/WFE instruction is executed at 128
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MHz from RAM. Then, 26 instead of 8 NOP instructions needs to be
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executed after WFI/WFE. This extension is not enabled by default.
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config SOC_NRF53_RTC_PRETICK
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bool "Pre-tick workaround for nRF5340 anomaly 165"
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depends on (SYS_CLOCK_EXISTS && SOC_NRF5340_CPUNET) || SOC_NRF5340_CPUAPP
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select NRFX_DPPI
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select ARM_ON_ENTER_CPU_IDLE_HOOK if SOC_NRF5340_CPUNET
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select ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK if SOC_NRF5340_CPUNET
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help
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Indicates that the pre-tick workaround for the anomaly 165 that affects
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the nRF5340 SoC should be applied. The workaround applies to wake ups caused
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by EVENTS_COMPARE and EVENTS_OVRFLW on RTC0 and RTC1 for which interrupts are
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enabled through INTENSET register. The case when these events are generated
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by EVTEN but without interrupts enabled through INTENSET is not handled.
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The EVENTS_TICK event is not handled.
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if SOC_NRF53_RTC_PRETICK
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config SOC_NRF53_RTC_PRETICK_IPC_CH_FROM_NET
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int "IPC 0 channel for RTC pretick"
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range 0 15
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default 10
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config SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET
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int "IPC 1 channel for RTC pretick"
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range 0 15
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default 11
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endif
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if SOC_NRF5340_CPUAPP
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config SOC_DCDC_NRF53X_APP
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bool
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imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
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help
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Enable nRF53 series System on Chip Application MCU DC/DC converter.
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config SOC_DCDC_NRF53X_NET
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bool
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imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
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help
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Enable nRF53 series System on Chip Network MCU DC/DC converter.
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config SOC_DCDC_NRF53X_HV
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bool
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help
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Enable nRF53 series System on Chip High Voltage DC/DC converter.
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config NRF_SPU_FLASH_REGION_SIZE
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hex
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default 0x4000
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help
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FLASH region size for the NRF_SPU peripheral
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config NRF_SPU_RAM_REGION_SIZE
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hex
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default 0x2000
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help
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RAM region size for the NRF_SPU peripheral
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config SOC_NRF_GPIO_FORWARDER_FOR_NRF5340
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bool
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depends on NRF_SOC_SECURE_SUPPORTED
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help
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hidden option for including the nRF GPIO pin forwarding
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if !TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM
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config SOC_ENABLE_LFXO
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bool "LFXO"
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default y
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help
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Enable the low-frequency oscillator (LFXO) functionality on XL1 and
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XL2 pins.
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This option must be enabled if either application or network core is
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to use the LFXO. Otherwise, XL1 and XL2 pins will behave as regular
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GPIOs.
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choice SOC_LFXO_LOAD_CAPACITANCE
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prompt "LFXO load capacitance"
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depends on SOC_ENABLE_LFXO
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default SOC_LFXO_CAP_INT_7PF
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config SOC_LFXO_CAP_EXTERNAL
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bool "Use external load capacitors"
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config SOC_LFXO_CAP_INT_6PF
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bool "6 pF internal load capacitance"
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config SOC_LFXO_CAP_INT_7PF
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bool "7 pF internal load capacitance"
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config SOC_LFXO_CAP_INT_9PF
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bool "9 pF internal load capacitance"
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endchoice
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choice SOC_HFXO_LOAD_CAPACITANCE
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prompt "HFXO load capacitance"
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default SOC_HFXO_CAP_DEFAULT
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config SOC_HFXO_CAP_DEFAULT
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bool "SoC default"
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help
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When this option is used, the SoC initialization routine does not
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touch the XOSC32MCAPS register value, so the default setting for
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the SoC is in effect. Please note that this may not necessarily be
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the reset value (0) for the register, as the register can be set
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during the device trimming in the SystemInit() function.
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config SOC_HFXO_CAP_EXTERNAL
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bool "Use external load capacitors"
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config SOC_HFXO_CAP_INTERNAL
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bool "Use internal load capacitors"
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depends on NRF_SOC_SECURE_SUPPORTED
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endchoice
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config SOC_HFXO_CAP_INT_VALUE_X2
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int "Doubled value of HFXO internal load capacitors (in pF)"
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depends on SOC_HFXO_CAP_INTERNAL
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range 14 40
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help
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Internal capacitors ranging from 7.0 pF to 20.0 pF in 0.5 pF steps
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can be enabled on pins XC1 and XC2. This option specifies doubled
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capacitance value for the two capacitors. Set it to 14 to get 7.0 pF
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for each capacitor, 15 to get 7.5 pF, and so on.
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endif # !TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM
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endif # SOC_NRF5340_CPUAPP
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config NRF_ENABLE_CACHE
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bool "Cache"
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depends on (SOC_NRF5340_CPUAPP && (!TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM)) \
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|| SOC_NRF5340_CPUNET
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default y
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help
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Instruction and Data cache is available on nRF5340 CPUAPP
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(Application MCU). It may only be accessed by Secure code.
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Instruction cache only (I-Cache) is available in nRF5340
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CPUNET (Network MCU).
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config BUILD_WITH_TFM
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# TF-M nRF53 platform enables the cache unconditionally.
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select NRF_ENABLE_CACHE if SOC_NRF5340_CPUAPP
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rsource "Kconfig.sync_rtc"
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endif # SOC_SERIES_NRF53X
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