725 lines
17 KiB
Plaintext
725 lines
17 KiB
Plaintext
/*
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* Copyright 2022-2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv8-r.dtsi>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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#include <zephyr/dt-bindings/clock/nxp_s32z2_clock.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-r52";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-r52";
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reg = <1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-r52";
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reg = <2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-r52";
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reg = <3>;
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};
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cpu@4 {
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device_type = "cpu";
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compatible = "arm,cortex-r52";
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reg = <4>;
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};
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cpu@5 {
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device_type = "cpu";
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compatible = "arm,cortex-r52";
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reg = <5>;
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};
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cpu@6 {
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device_type = "cpu";
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compatible = "arm,cortex-r52";
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reg = <6>;
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};
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cpu@7 {
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device_type = "cpu";
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compatible = "arm,cortex-r52";
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reg = <7>;
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};
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};
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arch_timer: timer {
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compatible = "arm,armv8_timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&gic>;
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};
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/* Dummy pinctrl node, filled with pin mux options at board level */
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pinctrl: pinctrl {
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compatible = "nxp,s32ze-pinctrl";
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status = "okay";
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};
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soc {
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interrupt-parent = <&gic>;
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clock: clock-controller@40030000 {
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compatible = "nxp,s32-clock";
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reg = <0x40030000 0x10000>,
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<0x40200000 0x10000>,
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<0x40210000 0x10000>,
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<0x40220000 0x10000>,
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<0x40260000 0x10000>,
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<0x40270000 0x10000>,
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<0x40830000 0x10000>,
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<0x41030000 0x10000>,
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<0x41830000 0x10000>,
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<0x42030000 0x10000>,
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<0x42830000 0x10000>,
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<0x44030000 0x10000>,
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<0x440a0000 0x10000>;
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#clock-cells = <1>;
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status = "okay";
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};
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gic: interrupt-controller@47800000 {
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compatible = "arm,gic-v3", "arm,gic";
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reg = <0x47800000 0x10000>,
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<0x47900000 0x80000>;
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interrupt-controller;
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#interrupt-cells = <4>;
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status = "okay";
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};
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sram0: memory@31780000 {
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compatible = "mmio-sram";
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reg = <0x31780000 DT_SIZE_M(1)>;
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};
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sram1: memory@35780000 {
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compatible = "mmio-sram";
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reg = <0x35780000 DT_SIZE_M(1)>;
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};
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uart0: uart@40170000 {
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compatible = "nxp,s32-linflexd";
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reg = <0x40170000 0x1000>;
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interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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uart1: uart@40180000 {
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compatible = "nxp,s32-linflexd";
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reg = <0x40180000 0x1000>;
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interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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uart2: uart@40190000 {
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compatible = "nxp,s32-linflexd";
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reg = <0x40190000 0x1000>;
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interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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uart3: uart@40970000 {
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compatible = "nxp,s32-linflexd";
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reg = <0x40970000 0x1000>;
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interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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uart4: uart@40980000 {
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compatible = "nxp,s32-linflexd";
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reg = <0x40980000 0x1000>;
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interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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uart5: uart@40990000 {
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compatible = "nxp,s32-linflexd";
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reg = <0x40990000 0x1000>;
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interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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uart6: uart@42170000 {
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compatible = "nxp,s32-linflexd";
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reg = <0x42170000 0x1000>;
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interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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uart7: uart@42180000 {
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compatible = "nxp,s32-linflexd";
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reg = <0x42180000 0x1000>;
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interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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uart8: uart@42190000 {
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compatible = "nxp,s32-linflexd";
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reg = <0x42190000 0x1000>;
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interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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uart9: uart@42980000 {
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compatible = "nxp,s32-linflexd";
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reg = <0x42980000 0x1000>;
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interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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uart10: uart@42990000 {
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compatible = "nxp,s32-linflexd";
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reg = <0x42990000 0x1000>;
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interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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uart11: uart@429a0000 {
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compatible = "nxp,s32-linflexd";
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reg = <0x429a0000 0x1000>;
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interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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uart12: uart@40330000 {
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compatible = "nxp,s32-linflexd";
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reg = <0x40330000 0x1000>;
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interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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siul2_0: siul2@40520000 {
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reg = <0x40520000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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eirq0: eirq0@40520010 {
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compatible = "nxp,s32-siul2-eirq";
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reg = <0x40520010 0x04>, <0x40520018 0x04>;
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reg-names = "disr0", "direr0";
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interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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gpioa: gpio@40521702 {
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compatible = "nxp,s32-gpio";
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reg = <0x40521702 0x02>, <0x40520240 0x40>;
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reg-names = "pgpdo", "mscr";
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interrupt-parent = <&eirq0>;
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interrupts = <1 1>, <3 0>, <5 2>, <12 3>,
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<13 4>, <14 5>, <15 6>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpiob: gpio@40521700 {
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compatible = "nxp,s32-gpio";
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reg = <0x40521700 0x02>, <0x40520280 0x40>;
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reg-names = "pgpdo", "mscr";
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interrupt-parent = <&eirq0>;
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interrupts = <0 7>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <15>;
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status = "disabled";
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};
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gpioo: gpio@40521716 {
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compatible = "nxp,s32-gpio";
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reg = <0x40521716 0x02>, <0x405204c0 0x40>;
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reg-names = "pgpdo", "mscr";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <14>;
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gpio-reserved-ranges = <0 10>;
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status = "disabled";
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};
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};
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siul2_1: siul2@40d20000 {
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reg = <0x40d20000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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eirq1: eirq1@40d20010 {
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compatible = "nxp,s32-siul2-eirq";
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reg = <0x40d20010 0x04>, <0x40d20018 0x04>;
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reg-names = "disr0", "direr0";
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interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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gpioc: gpio@40d21700 {
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compatible = "nxp,s32-gpio";
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reg = <0x40d21700 0x02>, <0x40d20280 0x40>;
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reg-names = "pgpdo", "mscr";
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interrupt-parent = <&eirq1>;
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interrupts = <3 0>, <5 1>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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gpio-reserved-ranges = <0 15>;
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status = "disabled";
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};
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gpiod: gpio@40d21706 {
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compatible = "nxp,s32-gpio";
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reg = <0x40d21706 0x02>, <0x40d202c0 0x40>;
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reg-names = "pgpdo", "mscr";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpioe: gpio@40d21704 {
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compatible = "nxp,s32-gpio";
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reg = <0x40d21704 0x02>, <0x40d20300 0x40>;
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reg-names = "pgpdo", "mscr";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpiof: gpio@40d2170a {
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compatible = "nxp,s32-gpio";
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reg = <0x40d2170a 0x02>, <0x40d20340 0x40>;
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reg-names = "pgpdo", "mscr";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpiog: gpio@40d21708 {
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compatible = "nxp,s32-gpio";
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reg = <0x40d21708 0x02>, <0x40d20380 0x40>;
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reg-names = "pgpdo", "mscr";
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interrupt-parent = <&eirq1>;
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interrupts = <0 2>, <1 3>, <4 4>,
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<5 5>, <10 6>, <11 7>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <12>;
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status = "disabled";
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};
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};
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siul2_3: siul2@41d20000 {
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reg = <0x41d20000 0x10000>;
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};
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siul2_4: siul2@42520000 {
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reg = <0x42520000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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eirq4: eirq4@42520010 {
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compatible = "nxp,s32-siul2-eirq";
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reg = <0x42520010 0x04>, <0x42520018 0x04>;
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reg-names = "disr0", "direr0";
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interrupts = <GIC_SPI 516 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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gpioh: gpio@42521708 {
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compatible = "nxp,s32-gpio";
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reg = <0x42521708 0x02>, <0x42520380 0x40>;
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reg-names = "pgpdo", "mscr";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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gpio-reserved-ranges = <0 12>;
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status = "disabled";
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};
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gpioi: gpio@4252170e {
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compatible = "nxp,s32-gpio";
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reg = <0x4252170e 0x02>, <0x425203c0 0x40>;
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reg-names = "pgpdo", "mscr";
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interrupt-parent = <&eirq4>;
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interrupts = <11 0>, <13 1>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpioj: gpio@4252170c {
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compatible = "nxp,s32-gpio";
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reg = <0x4252170c 0x02>, <0x42520400 0x40>;
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reg-names = "pgpdo", "mscr";
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interrupt-parent = <&eirq4>;
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interrupts = <12 2>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpiok: gpio@42521712 {
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compatible = "nxp,s32-gpio";
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reg = <0x42521712 0x02>, <0x42520440 0x40>;
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reg-names = "pgpdo", "mscr";
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interrupt-parent = <&eirq4>;
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interrupts = <4 3>, <6 4>, <9 5>,
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<11 6>, <13 7>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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gpiol: gpio@42521710 {
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compatible = "nxp,s32-gpio";
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reg = <0x42521710 0x02>, <0x42520480 0x40>;
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reg-names = "disr0", "direr0";
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reg-names = "pgpdo", "mscr";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <2>;
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status = "disabled";
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};
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};
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siul2_5: siul2@42d20000 {
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reg = <0x42d20000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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eirq5: eirq5@42d20010 {
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compatible = "nxp,s32-siul2-eirq";
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reg = <0x42d20010 0x04>, <0x42d20018 0x04>;
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reg-names = "disr0", "direr0";
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interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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gpiom: gpio@42d21710 {
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compatible = "nxp,s32-gpio";
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reg = <0x42d21710 0x02>, <0x42d20480 0x40>;
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reg-names = "pgpdo", "mscr";
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interrupt-parent = <&eirq5>;
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interrupts = <1 0>, <3 1>, <5 2>, <7 3>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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gpio-reserved-ranges = <0 2>;
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status = "disabled";
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};
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gpion: gpio@42d21716 {
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compatible = "nxp,s32-gpio";
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reg = <0x42d21716 0x02>, <0x42d204c0 0x40>;
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reg-names = "pgpdo", "mscr";
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interrupt-parent = <&eirq5>;
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interrupts = <0 4>, <2 5>, <5 6>, <6 7>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <10>;
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status = "disabled";
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};
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};
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spi0: spi@40130000 {
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compatible = "nxp,s32-spi";
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reg = <0x40130000 0x10000>;
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interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_SPI0_CLK>;
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num-cs = <5>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi1: spi@40140000 {
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compatible = "nxp,s32-spi";
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reg = <0x40140000 0x10000>;
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interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_SPI1_CLK>;
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num-cs = <5>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi2: spi@40930000 {
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compatible = "nxp,s32-spi";
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reg = <0x40930000 0x10000>;
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interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_SPI2_CLK>;
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num-cs = <5>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi3: spi@40940000 {
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compatible = "nxp,s32-spi";
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reg = <0x40940000 0x10000>;
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interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_SPI3_CLK>;
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num-cs = <5>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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|
};
|
|
|
|
spi4: spi@40950000 {
|
|
compatible = "nxp,s32-spi";
|
|
reg = <0x40950000 0x10000>;
|
|
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
|
clocks = <&clock NXP_S32_SPI4_CLK>;
|
|
num-cs = <5>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi5: spi@42130000 {
|
|
compatible = "nxp,s32-spi";
|
|
reg = <0x42130000 0x10000>;
|
|
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
|
clocks = <&clock NXP_S32_SPI5_CLK>;
|
|
num-cs = <5>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi6: spi@42140000 {
|
|
compatible = "nxp,s32-spi";
|
|
reg = <0x42140000 0x10000>;
|
|
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
|
clocks = <&clock NXP_S32_SPI6_CLK>;
|
|
num-cs = <5>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi7: spi@42150000 {
|
|
compatible = "nxp,s32-spi";
|
|
reg = <0x42150000 0x10000>;
|
|
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
|
clocks = <&clock NXP_S32_SPI7_CLK>;
|
|
num-cs = <5>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi8: spi@42930000 {
|
|
compatible = "nxp,s32-spi";
|
|
reg = <0x42930000 0x10000>;
|
|
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
|
clocks = <&clock NXP_S32_SPI8_CLK>;
|
|
num-cs = <5>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi9: spi@42940000 {
|
|
compatible = "nxp,s32-spi";
|
|
reg = <0x42940000 0x10000>;
|
|
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
|
clocks = <&clock NXP_S32_SPI9_CLK>;
|
|
num-cs = <5>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mru0: mbox@76070000 {
|
|
compatible = "nxp,s32-mru";
|
|
reg = <0x76070000 0x10000>;
|
|
interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
|
#mbox-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mru1: mbox@76090000 {
|
|
compatible = "nxp,s32-mru";
|
|
reg = <0x76090000 0x10000>;
|
|
interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
|
#mbox-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mru2: mbox@76270000 {
|
|
compatible = "nxp,s32-mru";
|
|
reg = <0x76270000 0x10000>;
|
|
interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
|
#mbox-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mru3: mbox@76290000 {
|
|
compatible = "nxp,s32-mru";
|
|
reg = <0x76290000 0x10000>;
|
|
interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
|
#mbox-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mru4: mbox@76870000 {
|
|
compatible = "nxp,s32-mru";
|
|
reg = <0x76870000 0x10000>;
|
|
interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
|
#mbox-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mru5: mbox@76890000 {
|
|
compatible = "nxp,s32-mru";
|
|
reg = <0x76890000 0x10000>;
|
|
interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
|
#mbox-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mru6: mbox@76a70000 {
|
|
compatible = "nxp,s32-mru";
|
|
reg = <0x76a70000 0x10000>;
|
|
interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
|
#mbox-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mru7: mbox@76a90000 {
|
|
compatible = "nxp,s32-mru";
|
|
reg = <0x76a90000 0x10000>;
|
|
interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
|
#mbox-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
netc: ethernet@74000000 {
|
|
reg = <0x74000000 0x1000000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
emdio: mdio@74b60000 {
|
|
compatible = "nxp,s32-netc-emdio";
|
|
reg = <0x74b60000 0x1c44>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
enetc_psi0: ethernet@74b00000 {
|
|
compatible = "nxp,s32-netc-psi";
|
|
reg = <0x74b00000 0x10000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
enetc_vsi1: ethernet@74bc0000 {
|
|
compatible = "nxp,s32-netc-vsi";
|
|
reg = <0x74bc0000 0x10000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
enetc_vsi2: ethernet@74bd0000 {
|
|
compatible = "nxp,s32-netc-vsi";
|
|
reg = <0x74bd0000 0x10000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
enetc_vsi3: ethernet@74be0000 {
|
|
compatible = "nxp,s32-netc-vsi";
|
|
reg = <0x74be0000 0x10000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
enetc_vsi4: ethernet@74bf0000 {
|
|
compatible = "nxp,s32-netc-vsi";
|
|
reg = <0x74bf0000 0x10000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
enetc_vsi5: ethernet@74c00000 {
|
|
compatible = "nxp,s32-netc-vsi";
|
|
reg = <0x74c00000 0x10000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
enetc_vsi6: ethernet@74c10000 {
|
|
compatible = "nxp,s32-netc-vsi";
|
|
reg = <0x74c10000 0x10000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
enetc_vsi7: ethernet@74c20000 {
|
|
compatible = "nxp,s32-netc-vsi";
|
|
reg = <0x74c20000 0x10000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
can0: can@4741b000 {
|
|
compatible = "nxp,s32-canxl";
|
|
reg = <0x4741b000 0x1000>,
|
|
<0x47426000 0x1000>,
|
|
<0x47424000 0x1000>,
|
|
<0x47423000 0x1000>,
|
|
<0x47425000 0x1000>;
|
|
reg-names = "sic", "grp_ctrl", "dsc_ctrl", "rx_fifo", "rx_fifo_ctrl";
|
|
status = "disabled";
|
|
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
|
|
<GIC_SPI 225 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
|
interrupt-names = "rx_tx", "error";
|
|
clocks = <&clock NXP_S32_P5_CANXL_PE_CLK>;
|
|
};
|
|
|
|
can1: can@4751b000 {
|
|
compatible = "nxp,s32-canxl";
|
|
reg = <0x4751b000 0x1000>,
|
|
<0x47526000 0x1000>,
|
|
<0x47524000 0x1000>,
|
|
<0x47523000 0x1000>,
|
|
<0x47525000 0x1000>;
|
|
reg-names = "sic", "grp_ctrl", "dsc_ctrl", "rx_fifo", "rx_fifo_ctrl";
|
|
status = "disabled";
|
|
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
|
|
<GIC_SPI 227 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
|
interrupt-names = "rx_tx", "error";
|
|
clocks = <&clock NXP_S32_P5_CANXL_PE_CLK>;
|
|
};
|
|
};
|
|
};
|