660 lines
18 KiB
Plaintext
660 lines
18 KiB
Plaintext
/*
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* Copyright (c) 2018, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/rdc/imx_rdc.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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status = "disabled";
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-m4f";
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reg = <1>;
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};
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};
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tcml:memory@1fff8000 {
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compatible = "nxp,imx-itcm";
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reg = <0x1fff8000 DT_SIZE_K(32)>;
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};
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tcmu:memory@20000000 {
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compatible = "nxp,imx-dtcm";
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reg = <0x20000000 DT_SIZE_K(32)>;
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};
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ocram_s:memory@208f8000 {
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device_type = "memory";
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compatible = "nxp,imx-sys-bus";
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reg = <0x208f8000 DT_SIZE_K(16)>;
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};
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ocram:memory@20900000 {
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device_type = "memory";
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compatible = "nxp,imx-sys-bus";
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reg = <0x20900000 DT_SIZE_K(128)>;
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};
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ddr:memory@80000000 {
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device_type = "memory";
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compatible = "nxp,imx-sys-bus";
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reg = <0x80000000 0x60000000>;
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};
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flash:memory@DT_FLASH_ADDR {
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compatible = "soc-nv-flash";
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reg = <DT_ADDR(DT_FLASH_ADDR) DT_FLASH_SIZE>;
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};
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sram:memory@DT_SRAM_ADDR {
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reg = <DT_ADDR(DT_SRAM_ADDR) DT_SRAM_SIZE>;
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};
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soc {
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uart1:uart@42020000 {
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compatible = "nxp,imx-uart";
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reg = <0x42020000 0x00004000>;
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interrupts = <26 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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status = "disabled";
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};
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uart2:uart@421e8000 {
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compatible = "nxp,imx-uart";
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reg = <0x421e8000 0x00004000>;
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interrupts = <27 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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status = "disabled";
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};
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uart3:uart@421ec000 {
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compatible = "nxp,imx-uart";
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reg = <0x421ec000 0x00004000>;
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interrupts = <28 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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status = "disabled";
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};
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uart4:uart@421f0000 {
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compatible = "nxp,imx-uart";
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reg = <0x421f0000 0x00004000>;
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interrupts = <29 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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status = "disabled";
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};
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uart5:uart@421f4000 {
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compatible = "nxp,imx-uart";
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reg = <0x421f4000 0x00004000>;
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interrupts = <30 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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status = "disabled";
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};
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uart6:uart@422a0000 {
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compatible = "nxp,imx-uart";
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reg = <0x422a0000 0x00004000>;
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interrupts = <17 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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status = "disabled";
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};
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gpio1:gpio@4209c000 {
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compatible = "nxp,imx-gpio";
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reg = <0x4209c000 0x4000>;
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interrupts = <66 0>, <67 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio2:gpio@420a0000 {
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compatible = "nxp,imx-gpio";
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reg = <0x420a0000 0x4000>;
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interrupts = <68 0>, <69 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio3:gpio@420a4000 {
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compatible = "nxp,imx-gpio";
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reg = <0x420a4000 0x4000>;
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interrupts = <70 0>, <71 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio4:gpio@420a8000 {
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compatible = "nxp,imx-gpio";
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reg = <0x420a8000 0x4000>;
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interrupts = <72 0>, <73 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio5:gpio@420ac000 {
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compatible = "nxp,imx-gpio";
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reg = <0x420ac000 0x4000>;
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interrupts = <74 0>, <75 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio6:gpio@420b0000 {
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compatible = "nxp,imx-gpio";
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reg = <0x420b0000 0x4000>;
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interrupts = <76 0>, <77 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio7:gpio@420b4000 {
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compatible = "nxp,imx-gpio";
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reg = <0x420b4000 0x4000>;
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interrupts = <78 0>, <79 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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mub:mu@4229c000 {
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compatible = "nxp,imx-mu";
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reg = <0x4229c000 0x4000>;
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interrupts = <99 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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status = "disabled";
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};
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epit1:epit@420d0000 {
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compatible = "nxp,imx-epit";
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reg = <0x420d0000 0x4000>;
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interrupts = <56 0>;
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prescaler = <0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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status = "disabled";
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};
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iomuxc: iomuxc@420e0000 {
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compatible = "nxp,imx-iomuxc";
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reg = <0x420e0000 0x4000>;
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status = "okay";
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pinctrl: pinctrl {
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status = "okay";
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/* iMX6 has same IOMUXC IP block as RT10xx series */
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compatible = "nxp,mcux-rt-pinctrl";
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};
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};
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epit2:epit@420d4000 {
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compatible = "nxp,imx-epit";
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reg = <0x420d4000 0x4000>;
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interrupts = <57 0>;
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prescaler = <0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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status = "disabled";
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};
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i2c1: i2c@421a0000 {
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compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x421a0000 0x4000>;
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interrupts = <36 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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status = "disabled";
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};
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i2c2: i2c@421a4000 {
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compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x421a4000 0x4000>;
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interrupts = <37 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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status = "disabled";
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};
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i2c3: i2c@421a8000 {
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compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x421a8000 0x4000>;
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interrupts = <38 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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status = "disabled";
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};
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i2c4: i2c@421f8000 {
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compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x421f8000 0x4000>;
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interrupts = <35 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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status = "disabled";
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};
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pwm1: pwm@42080000 {
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compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
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reg = <0x42080000 0x4000>;
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interrupts = <83 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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prescaler = <0>;
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#pwm-cells = <2>;
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status = "disabled";
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};
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pwm2: pwm@42084000 {
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compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
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reg = <0x42084000 0x4000>;
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interrupts = <84 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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prescaler = <0>;
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#pwm-cells = <2>;
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status = "disabled";
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};
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pwm3: pwm@42088000 {
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compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
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reg = <0x42088000 0x4000>;
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interrupts = <85 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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prescaler = <0>;
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#pwm-cells = <2>;
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status = "disabled";
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};
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pwm4: pwm@4208c000 {
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compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
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reg = <0x4208c000 0x4000>;
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interrupts = <86 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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prescaler = <0>;
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#pwm-cells = <2>;
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status = "disabled";
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};
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pwm5: pwm@422a4000 {
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compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
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reg = <0x422a4000 0x4000>;
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interrupts = <83 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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prescaler = <0>;
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#pwm-cells = <2>;
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status = "disabled";
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};
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pwm6: pwm@422a8000 {
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compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
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reg = <0x422a8000 0x4000>;
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interrupts = <84 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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prescaler = <0>;
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#pwm-cells = <2>;
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status = "disabled";
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};
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pwm7: pwm@422ac000 {
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compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
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reg = <0x422ac000 0x4000>;
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interrupts = <85 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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prescaler = <0>;
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#pwm-cells = <2>;
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status = "disabled";
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};
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pwm8: pwm@422ab000 {
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compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
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reg = <0x422ab000 0x4000>;
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interrupts = <86 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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prescaler = <0>;
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#pwm-cells = <2>;
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status = "disabled";
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};
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adc1: adc@42280000 {
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compatible = "nxp,vf610-adc";
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reg = <0x42280000 0x4000>;
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clk-source = <1>;
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clk-divider = <2>;
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interrupts = <100 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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adc2: adc@42284000 {
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compatible = "nxp,vf610-adc";
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reg = <0x42284000 0x4000>;
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clk-source = <1>;
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clk-divider = <2>;
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interrupts = <101 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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/*
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* GPIO pinmux options. These options define the pinmux settings
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* for GPIO ports on the package, so that the GPIO driver can
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* select GPIO mux options during GPIO configuration.
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*/
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&gpio1 {
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pinmux = <&mx6sx_pad_gpio1_io00__gpio1_io_0>,
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<&mx6sx_pad_gpio1_io01__gpio1_io_1>,
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<&mx6sx_pad_gpio1_io02__gpio1_io_2>,
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<&mx6sx_pad_gpio1_io03__gpio1_io_3>,
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<&mx6sx_pad_gpio1_io04__gpio1_io_4>,
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<&mx6sx_pad_gpio1_io05__gpio1_io_5>,
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<&mx6sx_pad_gpio1_io06__gpio1_io_6>,
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<&mx6sx_pad_gpio1_io07__gpio1_io_7>,
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<&mx6sx_pad_gpio1_io08__gpio1_io_8>,
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<&mx6sx_pad_gpio1_io09__gpio1_io_9>,
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<&mx6sx_pad_gpio1_io10__gpio1_io_10>,
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<&mx6sx_pad_gpio1_io11__gpio1_io_11>,
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<&mx6sx_pad_gpio1_io12__gpio1_io_12>,
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<&mx6sx_pad_gpio1_io13__gpio1_io_13>,
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<&mx6sx_pad_csi_data00__gpio1_io_14>,
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<&mx6sx_pad_csi_data01__gpio1_io_15>,
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<&mx6sx_pad_csi_data02__gpio1_io_16>,
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<&mx6sx_pad_csi_data03__gpio1_io_17>,
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<&mx6sx_pad_csi_data04__gpio1_io_18>,
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<&mx6sx_pad_csi_data05__gpio1_io_19>,
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<&mx6sx_pad_csi_data06__gpio1_io_20>,
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<&mx6sx_pad_csi_data07__gpio1_io_21>,
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<&mx6sx_pad_csi_hsync__gpio1_io_22>,
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<&mx6sx_pad_csi_mclk__gpio1_io_23>,
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<&mx6sx_pad_csi_pixclk__gpio1_io_24>,
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<&mx6sx_pad_csi_vsync__gpio1_io_25>;
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};
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&gpio2 {
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pinmux = <&mx6sx_pad_enet1_col__gpio2_io_0>,
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<&mx6sx_pad_enet1_crs__gpio2_io_1>,
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<&mx6sx_pad_enet1_mdc__gpio2_io_2>,
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<&mx6sx_pad_enet1_mdio__gpio2_io_3>,
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<&mx6sx_pad_enet1_rx_clk__gpio2_io_4>,
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<&mx6sx_pad_enet1_tx_clk__gpio2_io_5>,
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<&mx6sx_pad_enet2_col__gpio2_io_6>,
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<&mx6sx_pad_enet2_crs__gpio2_io_7>,
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<&mx6sx_pad_enet2_rx_clk__gpio2_io_8>,
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<&mx6sx_pad_enet2_tx_clk__gpio2_io_9>,
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<&mx6sx_pad_key_col0__gpio2_io_10>,
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<&mx6sx_pad_key_col1__gpio2_io_11>,
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<&mx6sx_pad_key_col2__gpio2_io_12>,
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<&mx6sx_pad_key_col3__gpio2_io_13>,
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<&mx6sx_pad_key_col4__gpio2_io_14>,
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<&mx6sx_pad_key_row0__gpio2_io_15>,
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<&mx6sx_pad_key_row1__gpio2_io_16>,
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<&mx6sx_pad_key_row2__gpio2_io_17>,
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<&mx6sx_pad_key_row3__gpio2_io_18>,
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<&mx6sx_pad_key_row4__gpio2_io_19>;
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};
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&gpio3 {
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pinmux = <&mx6sx_pad_lcd1_clk__gpio3_io_0>,
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<&mx6sx_pad_lcd1_data00__gpio3_io_1>,
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<&mx6sx_pad_lcd1_data01__gpio3_io_2>,
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<&mx6sx_pad_lcd1_data02__gpio3_io_3>,
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<&mx6sx_pad_lcd1_data03__gpio3_io_4>,
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<&mx6sx_pad_lcd1_data04__gpio3_io_5>,
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<&mx6sx_pad_lcd1_data05__gpio3_io_6>,
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<&mx6sx_pad_lcd1_data06__gpio3_io_7>,
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<&mx6sx_pad_lcd1_data07__gpio3_io_8>,
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<&mx6sx_pad_lcd1_data08__gpio3_io_9>,
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<&mx6sx_pad_lcd1_data09__gpio3_io_10>,
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<&mx6sx_pad_lcd1_data10__gpio3_io_11>,
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<&mx6sx_pad_lcd1_data11__gpio3_io_12>,
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<&mx6sx_pad_lcd1_data12__gpio3_io_13>,
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<&mx6sx_pad_lcd1_data13__gpio3_io_14>,
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<&mx6sx_pad_lcd1_data14__gpio3_io_15>,
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<&mx6sx_pad_lcd1_data15__gpio3_io_16>,
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<&mx6sx_pad_lcd1_data16__gpio3_io_17>,
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<&mx6sx_pad_lcd1_data17__gpio3_io_18>,
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<&mx6sx_pad_lcd1_data18__gpio3_io_19>,
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<&mx6sx_pad_lcd1_data19__gpio3_io_20>,
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<&mx6sx_pad_lcd1_data20__gpio3_io_21>,
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<&mx6sx_pad_lcd1_data21__gpio3_io_22>,
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<&mx6sx_pad_lcd1_data22__gpio3_io_23>,
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<&mx6sx_pad_lcd1_data23__gpio3_io_24>,
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<&mx6sx_pad_lcd1_enable__gpio3_io_25>,
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<&mx6sx_pad_lcd1_hsync__gpio3_io_26>,
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<&mx6sx_pad_lcd1_reset__gpio3_io_27>,
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<&mx6sx_pad_lcd1_vsync__gpio3_io_28>;
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};
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&gpio4 {
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pinmux = <&mx6sx_pad_nand_ale__gpio4_io_0>,
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<&mx6sx_pad_nand_ce0_b__gpio4_io_1>,
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<&mx6sx_pad_nand_ce1_b__gpio4_io_2>,
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<&mx6sx_pad_nand_cle__gpio4_io_3>,
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<&mx6sx_pad_nand_data00__gpio4_io_4>,
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<&mx6sx_pad_nand_data01__gpio4_io_5>,
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<&mx6sx_pad_nand_data02__gpio4_io_6>,
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<&mx6sx_pad_nand_data03__gpio4_io_7>,
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<&mx6sx_pad_nand_data04__gpio4_io_8>,
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<&mx6sx_pad_nand_data05__gpio4_io_9>,
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<&mx6sx_pad_nand_data06__gpio4_io_10>,
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<&mx6sx_pad_nand_data07__gpio4_io_11>,
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<&mx6sx_pad_nand_re_b__gpio4_io_12>,
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<&mx6sx_pad_nand_ready_b__gpio4_io_13>,
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<&mx6sx_pad_nand_we_b__gpio4_io_14>,
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<&mx6sx_pad_nand_wp_b__gpio4_io_15>,
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<&mx6sx_pad_qspi1a_data0__gpio4_io_16>,
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<&mx6sx_pad_qspi1a_data1__gpio4_io_17>,
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<&mx6sx_pad_qspi1a_data2__gpio4_io_18>,
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<&mx6sx_pad_qspi1a_data3__gpio4_io_19>,
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<&mx6sx_pad_qspi1a_dqs__gpio4_io_20>,
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<&mx6sx_pad_qspi1a_sclk__gpio4_io_21>,
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<&mx6sx_pad_qspi1a_ss0_b__gpio4_io_22>,
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<&mx6sx_pad_qspi1a_ss1_b__gpio4_io_23>,
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<&mx6sx_pad_qspi1b_data0__gpio4_io_24>,
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<&mx6sx_pad_qspi1b_data1__gpio4_io_25>,
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<&mx6sx_pad_qspi1b_data2__gpio4_io_26>,
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<&mx6sx_pad_qspi1b_data3__gpio4_io_27>,
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<&mx6sx_pad_qspi1b_dqs__gpio4_io_28>,
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<&mx6sx_pad_qspi1b_sclk__gpio4_io_29>,
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<&mx6sx_pad_qspi1b_ss0_b__gpio4_io_30>,
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<&mx6sx_pad_qspi1b_ss1_b__gpio4_io_31>;
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};
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&gpio5 {
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pinmux = <&mx6sx_pad_rgmii1_rd0__gpio5_io_0>,
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<&mx6sx_pad_rgmii1_rd1__gpio5_io_1>,
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<&mx6sx_pad_rgmii1_rd2__gpio5_io_2>,
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<&mx6sx_pad_rgmii1_rd3__gpio5_io_3>,
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<&mx6sx_pad_rgmii1_rx_ctl__gpio5_io_4>,
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<&mx6sx_pad_rgmii1_rxc__gpio5_io_5>,
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<&mx6sx_pad_rgmii1_td0__gpio5_io_6>,
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<&mx6sx_pad_rgmii1_td1__gpio5_io_7>,
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<&mx6sx_pad_rgmii1_td2__gpio5_io_8>,
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<&mx6sx_pad_rgmii1_td3__gpio5_io_9>,
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<&mx6sx_pad_rgmii1_tx_ctl__gpio5_io_10>,
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<&mx6sx_pad_rgmii1_txc__gpio5_io_11>,
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<&mx6sx_pad_rgmii2_rd0__gpio5_io_12>,
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<&mx6sx_pad_rgmii2_rd1__gpio5_io_13>,
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<&mx6sx_pad_rgmii2_rd2__gpio5_io_14>,
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<&mx6sx_pad_rgmii2_rd3__gpio5_io_15>,
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<&mx6sx_pad_rgmii2_rx_ctl__gpio5_io_16>,
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<&mx6sx_pad_rgmii2_rxc__gpio5_io_17>,
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<&mx6sx_pad_rgmii2_td0__gpio5_io_18>,
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<&mx6sx_pad_rgmii2_td1__gpio5_io_19>,
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<&mx6sx_pad_rgmii2_td2__gpio5_io_20>,
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<&mx6sx_pad_rgmii2_td3__gpio5_io_21>,
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<&mx6sx_pad_rgmii2_tx_ctl__gpio5_io_22>,
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<&mx6sx_pad_rgmii2_txc__gpio5_io_23>;
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};
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&gpio6 {
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pinmux = <&mx6sx_pad_sd1_clk__gpio6_io_0>,
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<&mx6sx_pad_sd1_cmd__gpio6_io_1>,
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<&mx6sx_pad_sd1_data0__gpio6_io_2>,
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<&mx6sx_pad_sd1_data1__gpio6_io_3>,
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<&mx6sx_pad_sd1_data2__gpio6_io_4>,
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<&mx6sx_pad_sd1_data3__gpio6_io_5>,
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<&mx6sx_pad_sd2_clk__gpio6_io_6>,
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<&mx6sx_pad_sd2_cmd__gpio6_io_7>,
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<&mx6sx_pad_sd2_data0__gpio6_io_8>,
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<&mx6sx_pad_sd2_data1__gpio6_io_9>,
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<&mx6sx_pad_sd2_data2__gpio6_io_10>,
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<&mx6sx_pad_sd2_data3__gpio6_io_11>,
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<&mx6sx_pad_sd4_clk__gpio6_io_12>,
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<&mx6sx_pad_sd4_cmd__gpio6_io_13>,
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<&mx6sx_pad_sd4_data0__gpio6_io_14>,
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<&mx6sx_pad_sd4_data1__gpio6_io_15>,
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<&mx6sx_pad_sd4_data2__gpio6_io_16>,
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<&mx6sx_pad_sd4_data3__gpio6_io_17>,
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<&mx6sx_pad_sd4_data4__gpio6_io_18>,
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<&mx6sx_pad_sd4_data5__gpio6_io_19>,
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<&mx6sx_pad_sd4_data6__gpio6_io_20>,
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<&mx6sx_pad_sd4_data7__gpio6_io_21>,
|
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<&mx6sx_pad_sd4_reset_b__gpio6_io_22>;
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};
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&gpio7 {
|
|
pinmux = <&mx6sx_pad_sd3_clk__gpio7_io_0>,
|
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<&mx6sx_pad_sd3_cmd__gpio7_io_1>,
|
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<&mx6sx_pad_sd3_data0__gpio7_io_2>,
|
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<&mx6sx_pad_sd3_data1__gpio7_io_3>,
|
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<&mx6sx_pad_sd3_data2__gpio7_io_4>,
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<&mx6sx_pad_sd3_data3__gpio7_io_5>,
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<&mx6sx_pad_sd3_data4__gpio7_io_6>,
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<&mx6sx_pad_sd3_data5__gpio7_io_7>,
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<&mx6sx_pad_sd3_data6__gpio7_io_8>,
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<&mx6sx_pad_sd3_data7__gpio7_io_9>,
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<&mx6sx_pad_usb_h_data__gpio7_io_10>,
|
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<&mx6sx_pad_usb_h_strobe__gpio7_io_11>;
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};
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