61 lines
1.2 KiB
C
61 lines
1.2 KiB
C
/*
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* Copyright (c) 2015 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_CACHE_H_
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#define ZEPHYR_INCLUDE_CACHE_H_
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#include <kernel.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define _sys_cache_flush_sig(x) void (x)(vaddr_t virt, size_t size)
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#if defined(CONFIG_CACHE_FLUSHING)
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#if defined(CONFIG_ARCH_CACHE_FLUSH_DETECT)
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typedef _sys_cache_flush_sig(_sys_cache_flush_t);
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extern _sys_cache_flush_t *sys_cache_flush;
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#else
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extern _sys_cache_flush_sig(sys_cache_flush);
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#endif
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#else
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/*
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* Provide NOP APIs for systems that do not have caches.
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*
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* An example is the Cortex-M chips. However, the functions are provided so
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* that code that need to manipulate caches can be written in an
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* architecture-agnostic manner. The functions do nothing. The cache line size
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* value is always 0.
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*/
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static inline _sys_cache_flush_sig(sys_cache_flush)
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{
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ARG_UNUSED(virt);
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ARG_UNUSED(size);
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/* do nothing */
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}
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#endif /* CACHE_FLUSHING */
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#if defined(CONFIG_CACHE_LINE_SIZE_DETECT)
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extern size_t sys_cache_line_size;
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#elif defined(CONFIG_CACHE_LINE_SIZE)
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#define sys_cache_line_size CONFIG_CACHE_LINE_SIZE
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#else
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#define sys_cache_line_size 0
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_INCLUDE_CACHE_H_ */
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