134 lines
3.1 KiB
Plaintext
134 lines
3.1 KiB
Plaintext
# Kconfig - ETH_ENC28J60 Ethernet driver configuration options
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#
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# Copyright (c) 2015 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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menuconfig ETH_ENC28J60
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bool "ENC28J60C Ethernet Controller"
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depends on NET_L2_ETHERNET
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depends on SPI
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help
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ENC28J60C Stand-Alone Ethernet Controller
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with SPI Interface
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config ETH_ENC28J60_RX_THREAD_STACK_SIZE
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int "Stack size for internal incoming packet handler"
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depends on ETH_ENC28J60
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default 800
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help
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Size of the stack used for internal thread which is ran for
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incoming packet processing.
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config ETH_ENC28J60_RX_THREAD_PRIO
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int "Priority for internal incoming packet handler"
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depends on ETH_ENC28J60
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default 2
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help
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Priority level for internal thread which is ran for incoming
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packet processing.
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config ETH_EN28J60_TIMEOUT
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int "IP buffer timeout"
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depends on ETH_ENC28J60
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default 100
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help
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Given timeout in milliseconds. Maximum amount of time
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that the driver will wait from the IP stack to get
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a memory buffer before the Ethernet frame is dropped.
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config ETH_ENC28J60_0
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bool "ENC28J60C Ethernet port 0"
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depends on ETH_ENC28J60
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help
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Include port 0 driver
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if ETH_ENC28J60 && ETH_ENC28J60_0
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config ETH_ENC28J60_0_NAME
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string "Driver's name"
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default "ETH_0"
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config ETH_EN28J60_0_FULL_DUPLEX
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bool "ENC28J60 full duplex"
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default y
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help
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Enable Full Duplex. Device is configured half duplex
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when disabled.
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config ETH_ENC28J60_0_GPIO_PORT_NAME
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string "GPIO controller port name"
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default "GPIO_0"
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help
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GPIO port name through which ENC28J60C interruption is received.
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config ETH_ENC28J60_0_GPIO_PIN
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int "ENC28J60C INT GPIO PIN"
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default 19
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help
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GPIO pin number used to connect INT
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config ETH_ENC28J60_0_SPI_PORT_NAME
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string "SPI master controller port name"
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default "SPI_0"
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help
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Master SPI port name through which ENC28J60C chip is accessed.
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config ETH_ENC28J60_0_SLAVE
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hex "ETH_ENC28J60 SPI slave select pin"
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default 1
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help
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ENC28J60C chip select pin.
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config ETH_ENC28J60_0_GPIO_SPI_CS
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bool "Manage SPI CS through a GPIO pin"
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help
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This option is useful if one needs to manage SPI CS through a GPIO
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pin to by-pass the SPI controller's CS logic.
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config ETH_ENC28J60_0_SPI_CS_PORT_NAME
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string "SPI cs port name"
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depends on ETH_ENC28J60_0_GPIO_SPI_CS
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help
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Master SPI port name through which ENC28J60C chip is accessed.
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config ETH_ENC28J60_0_SPI_CS_PIN
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int "SPI CS pin"
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default 0
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depends on ETH_ENC28J60_0_GPIO_SPI_CS
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help
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CS pin used for the SPI device
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config ETH_ENC28J60_0_SPI_BUS_FREQ
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int "ENC28J60C SPI bus speed in Hz"
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default 128000
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help
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This is the SPI bus frequency for accessing the device.
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config ETH_ENC28J60_0_MAC3
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hex "MAC Address Byte 3"
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default 0
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help
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MACADDR<0:23> are Microchip's OUI.
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This is the byte 3 of the MAC address.
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MACADDR<31:24>
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config ETH_ENC28J60_0_MAC4
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hex "MAC Address Byte 4"
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default 0
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help
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MACADDR<0:23> are Microchip's OUI.
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This is the byte 4 of the MAC address.
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MACADDR<40:32>
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config ETH_ENC28J60_0_MAC5
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hex "MAC Address Byte 5"
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default 0
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help
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MACADDR<0:23> are Microchip's OUI.
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This is the byte 5 of the MAC address.
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MACADDR<48:41>
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endif #ETH_ENC28J60 && ETH_ENC28J60_0
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