234 lines
6.1 KiB
C
234 lines
6.1 KiB
C
/*
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* Copyright (c) 2018 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <device.h>
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#include <errno.h>
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#include <init.h>
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#include <string.h>
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#include <soc.h>
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#include <dma.h>
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#include <altera_common.h>
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#include "altera_msgdma_csr_regs.h"
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#include "altera_msgdma_descriptor_regs.h"
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#include "altera_msgdma.h"
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#define SYS_LOG_LEVEL CONFIG_SYS_LOG_DMA_LEVEL
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#include <logging/sys_log.h>
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/* Device configuration parameters */
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struct nios2_msgdma_dev_cfg {
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alt_msgdma_dev *msgdma_dev;
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alt_msgdma_standard_descriptor desc;
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u32_t direction;
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struct k_sem sem_lock;
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void (*dma_callback)(struct device *dev, u32_t id,
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int error_code);
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};
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#define DEV_NAME(dev) ((dev)->config->name)
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#define DEV_CFG(dev) \
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((struct nios2_msgdma_dev_cfg *)(dev)->config->config_info)
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static void nios2_msgdma_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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struct nios2_msgdma_dev_cfg *cfg = DEV_CFG(dev);
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/* Call Altera HAL driver ISR */
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alt_handle_irq(cfg->msgdma_dev, MSGDMA_0_CSR_IRQ);
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}
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static void nios2_msgdma_callback(void *context)
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{
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struct nios2_msgdma_dev_cfg *dev_cfg =
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DEV_CFG((struct device *)context);
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int err_code;
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u32_t status;
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status = IORD_ALTERA_MSGDMA_CSR_STATUS(dev_cfg->msgdma_dev->csr_base);
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if (status & ALTERA_MSGDMA_CSR_STOPPED_ON_ERROR_MASK) {
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err_code = -EIO;
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} else if (status & ALTERA_MSGDMA_CSR_BUSY_MASK) {
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err_code = -EBUSY;
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} else {
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err_code = 0;
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}
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SYS_LOG_DBG("msgdma csr status Reg: 0x%x", status);
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dev_cfg->dma_callback((struct device *)context, 0, err_code);
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}
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static int nios2_msgdma_config(struct device *dev, u32_t channel,
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struct dma_config *cfg)
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{
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struct nios2_msgdma_dev_cfg *dev_cfg = DEV_CFG(dev);
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struct dma_block_config *dma_block;
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int status;
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u32_t control;
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/* Nios-II MSGDMA supports only one channel per DMA core */
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if (channel != 0) {
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SYS_LOG_ERR("invalid channel number");
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return -EINVAL;
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}
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#if MSGDMA_0_CSR_PREFETCHER_ENABLE
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if (cfg->block_count > 1) {
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SYS_LOG_ERR("driver yet add support multiple descriptors");
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return -EINVAL;
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}
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#else
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if (cfg->block_count != 1) {
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SYS_LOG_ERR("invalid block count!!");
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return -EINVAL;
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}
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#endif
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if (cfg->head_block == NULL) {
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SYS_LOG_ERR("head_block ptr NULL!!");
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return -EINVAL;
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}
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if (cfg->head_block->block_size > MSGDMA_0_DESCRIPTOR_SLAVE_MAX_BYTE) {
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SYS_LOG_ERR("DMA error: Data size too big: %d",
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cfg->head_block->block_size);
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return -EINVAL;
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}
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k_sem_take(&dev_cfg->sem_lock, K_FOREVER);
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dev_cfg->dma_callback = cfg->dma_callback;
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dev_cfg->direction = cfg->channel_direction;
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dma_block = cfg->head_block;
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control = ALTERA_MSGDMA_DESCRIPTOR_CONTROL_TRANSFER_COMPLETE_IRQ_MASK |
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ALTERA_MSGDMA_DESCRIPTOR_CONTROL_EARLY_TERMINATION_IRQ_MASK;
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if (dev_cfg->direction == MEMORY_TO_MEMORY) {
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status = alt_msgdma_construct_standard_mm_to_mm_descriptor(
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dev_cfg->msgdma_dev, &dev_cfg->desc,
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(alt_u32 *)dma_block->source_address,
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(alt_u32 *)dma_block->dest_address,
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dma_block->block_size,
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control);
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} else if (dev_cfg->direction == MEMORY_TO_PERIPHERAL) {
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status = alt_msgdma_construct_standard_mm_to_st_descriptor(
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dev_cfg->msgdma_dev, &dev_cfg->desc,
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(alt_u32 *)dma_block->source_address,
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dma_block->block_size,
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control);
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} else if (dev_cfg->direction == PERIPHERAL_TO_MEMORY) {
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status = alt_msgdma_construct_standard_st_to_mm_descriptor(
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dev_cfg->msgdma_dev, &dev_cfg->desc,
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(alt_u32 *)dma_block->dest_address,
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dma_block->block_size,
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control);
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} else {
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SYS_LOG_ERR("invalid channel direction");
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status = -EINVAL;
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}
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/* Register msgdma callback */
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alt_msgdma_register_callback(dev_cfg->msgdma_dev,
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nios2_msgdma_callback,
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ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK |
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ALTERA_MSGDMA_CSR_STOP_ON_ERROR_MASK |
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ALTERA_MSGDMA_CSR_STOP_ON_EARLY_TERMINATION_MASK,
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dev);
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/* Clear the IRQ status */
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IOWR_ALTERA_MSGDMA_CSR_STATUS(dev_cfg->msgdma_dev->csr_base,
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ALTERA_MSGDMA_CSR_IRQ_SET_MASK);
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k_sem_give(&dev_cfg->sem_lock);
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return status;
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}
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static int nios2_msgdma_transfer_start(struct device *dev, u32_t channel)
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{
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struct nios2_msgdma_dev_cfg *cfg = DEV_CFG(dev);
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int status;
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/* Nios-II mSGDMA supports only one channel per DMA core */
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if (channel != 0) {
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SYS_LOG_ERR("Invalid channel number");
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return -EINVAL;
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}
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k_sem_take(&cfg->sem_lock, K_FOREVER);
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status = alt_msgdma_standard_descriptor_async_transfer(cfg->msgdma_dev,
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&cfg->desc);
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k_sem_give(&cfg->sem_lock);
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if (status < 0) {
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SYS_LOG_ERR("DMA transfer error (%d)", status);
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}
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return status;
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}
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static int nios2_msgdma_transfer_stop(struct device *dev, u32_t channel)
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{
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struct nios2_msgdma_dev_cfg *cfg = DEV_CFG(dev);
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int ret = -EIO;
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u32_t status;
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k_sem_take(&cfg->sem_lock, K_FOREVER);
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/* Stop the DMA Dispatcher */
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IOWR_ALTERA_MSGDMA_CSR_CONTROL(cfg->msgdma_dev->csr_base,
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ALTERA_MSGDMA_CSR_STOP_MASK);
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status = IORD_ALTERA_MSGDMA_CSR_STATUS(cfg->msgdma_dev->csr_base);
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k_sem_give(&cfg->sem_lock);
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if (status & ALTERA_MSGDMA_CSR_STOP_STATE_MASK) {
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SYS_LOG_DBG("DMA Dispatcher stopped");
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ret = 0;
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}
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SYS_LOG_DBG("msgdma csr status Reg: 0x%x", status);
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return status;
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}
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static const struct dma_driver_api nios2_msgdma_driver_api = {
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.config = nios2_msgdma_config,
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.start = nios2_msgdma_transfer_start,
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.stop = nios2_msgdma_transfer_stop,
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};
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/* DMA0 */
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static struct device DEVICE_NAME_GET(dma0_nios2);
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static int nios2_msgdma0_initialize(struct device *dev)
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{
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struct nios2_msgdma_dev_cfg *dev_cfg = DEV_CFG(dev);
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/* Initialize semaphore */
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k_sem_init(&dev_cfg->sem_lock, 1, 1);
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alt_msgdma_init(dev_cfg->msgdma_dev, 0, MSGDMA_0_CSR_IRQ);
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IRQ_CONNECT(MSGDMA_0_CSR_IRQ, CONFIG_DMA_0_IRQ_PRI,
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nios2_msgdma_isr, DEVICE_GET(dma0_nios2), 0);
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irq_enable(MSGDMA_0_CSR_IRQ);
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return 0;
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}
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ALTERA_MSGDMA_CSR_DESCRIPTOR_SLAVE_INSTANCE(MSGDMA_0, MSGDMA_0_CSR,
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MSGDMA_0_DESCRIPTOR_SLAVE, msgdma_dev0)
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static struct nios2_msgdma_dev_cfg dma0_nios2_config = {
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.msgdma_dev = &msgdma_dev0,
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};
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DEVICE_AND_API_INIT(dma0_nios2, CONFIG_DMA_0_NAME, &nios2_msgdma0_initialize,
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NULL, &dma0_nios2_config, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&nios2_msgdma_driver_api);
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