120 lines
4.2 KiB
C
120 lines
4.2 KiB
C
/* aux_regs.h - ARCv2 auxiliary registers definitions */
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/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Wind River Systems nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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DESCRIPTION
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Definitions for auxiliary registers.
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*/
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#ifndef _ARC_V2_AUX_REGS__H_
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#define _ARC_V2_AUX_REGS__H_
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#define _ARC_V2_LP_START 0x002
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#define _ARC_V2_LP_END 0x003
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#define _ARC_V2_STATUS32 0x00a
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#define _ARC_V2_STATUS32_P0 0x00b
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#define _ARC_V2_AUX_IRQ_CTRL 0x00e
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#define _ARC_V2_IC_CTRL 0x011
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#define _ARC_V2_TMR0_COUNT 0x021
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#define _ARC_V2_TMR0_CONTROL 0x022
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#define _ARC_V2_TMR0_LIMIT 0x023
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#define _ARC_V2_AUX_IRQ_ACT 0x043
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#define _ARC_V2_TMR1_COUNT 0x100
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#define _ARC_V2_TMR1_CONTROL 0x101
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#define _ARC_V2_TMR1_LIMIT 0x102
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#define _ARC_V2_IRQ_PRIO_PEND 0x200
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#define _ARC_V2_AUX_IRQ_HINT 0x201
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#define _ARC_V2_IRQ_PRIORITY 0x206
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#define _ARC_V2_ERET 0x400
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#define _ARC_V2_ERSTATUS 0x402
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#define _ARC_V2_ECR 0x403
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#define _ARC_V2_EFA 0x404
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#define _ARC_V2_ICAUSE 0x40a
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#define _ARC_V2_IRQ_SELECT 0x40b
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#define _ARC_V2_IRQ_ENABLE 0x40c
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#define _ARC_V2_IRQ_TRIGGER 0x40d
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#define _ARC_V2_IRQ_STATUS 0x40f
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#define _ARC_V2_IRQ_PULSE_CANCEL 0x415
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#define _ARC_V2_IRQ_PENDING 0x416
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/* STATUS32/STATUS32_P0 bits */
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#define _ARC_V2_STATUS32_H (1 << 0)
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#define _ARC_V2_STATUS32_E(x) ((x) << 1)
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#define _ARC_V2_STATUS32_AE_BIT 5
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#define _ARC_V2_STATUS32_AE (1 << ARC_V2_STATUS32_AE_BIT)
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#define _ARC_V2_STATUS32_DE (1 << 6)
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#define _ARC_V2_STATUS32_U (1 << 7)
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#define _ARC_V2_STATUS32_V (1 << 8)
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#define _ARC_V2_STATUS32_C (1 << 9)
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#define _ARC_V2_STATUS32_N (1 << 10)
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#define _ARC_V2_STATUS32_Z (1 << 11)
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#define _ARC_V2_STATUS32_L (1 << 12)
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#define _ARC_V2_STATUS32_DZ (1 << 13)
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#define _ARC_V2_STATUS32_SC (1 << 14)
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#define _ARC_V2_STATUS32_ES (1 << 15)
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#define _ARC_V2_STATUS32_RB(x) ((x) << 16)
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#define _ARC_V2_STATUS32_IE (1 << 31)
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/* exception cause register masks */
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#define _ARC_V2_ECR_VECTOR(X) ((X & 0xff0000) >> 16)
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#define _ARC_V2_ECR_CODE(X) ((X & 0xff00) >> 8)
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#define _ARC_V2_ECR_PARAMETER(X) (X & 0xff)
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#ifndef _ASMLANGUAGE
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#if defined(__GNUC__)
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#define _arc_v2_aux_reg_read(reg) __builtin_arc_lr(reg)
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#define _arc_v2_aux_reg_write(reg, val) __builtin_arc_sr((unsigned int)val, reg)
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#else /* ! __GNUC__ */
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#define _arc_v2_aux_reg_read(reg) \
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({ \
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unsigned int __ret; \
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__asm__ __volatile__(" lr 0, [%1]" \
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: "=r"(__ret) \
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: "i"(reg)); \
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__ret; \
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})
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#define _arc_v2_aux_reg_write(reg, val) \
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({ \
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__asm__ __volatile__(" sr %0, [%1]" \
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: \
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: "ir"(val), "i"(reg)); \
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})
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#endif /* __GNUC__ */
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#endif /* _ASMLANGUAGE */
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#endif /* _ARC_V2_AUX_REGS__H_ */
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