zephyr/tests/arch/riscv
Nicolas Pitre 373f8acaa7 tests: riscv: test FPU sharing access behavior
The RISC-V FPU context switching code is intricate and sometimes subtle.
Here's a test that exercizes various code paths to ensure they work as
intended, and to confirm that the target hardware does behave as
expected too.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2023-01-30 23:47:36 +00:00
..
fpu_sharing