258 lines
6.1 KiB
C
258 lines
6.1 KiB
C
/*
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* Copyright (c) 2018 SiFive Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <logging/log.h>
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LOG_MODULE_REGISTER(pwm_sifive, CONFIG_PWM_LOG_LEVEL);
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#include <sys/sys_io.h>
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#include <device.h>
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#include <drivers/pwm.h>
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/* Macros */
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#define PWM_REG(z_config, _offset) ((mem_addr_t) ((z_config)->base + _offset))
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/* Register Offsets */
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#define REG_PWMCFG 0x00
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#define REG_PWMCOUNT 0x08
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#define REG_PWMS 0x10
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#define REG_PWMCMP0 0x20
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#define REG_PWMCMP(_channel) (REG_PWMCMP0 + ((_channel) * 0x4))
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/* Number of PWM Channels */
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#define SF_NUMCHANNELS 4
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/* pwmcfg Bit Offsets */
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#define SF_PWMSTICKY 8
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#define SF_PWMZEROCMP 9
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#define SF_PWMDEGLITCH 10
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#define SF_PWMENALWAYS 12
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#define SF_PWMENONESHOT 13
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#define SF_PWMCMPCENTER(_channel) (16 + (_channel))
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#define SF_PWMCMPGANG(_channel) (24 + (_channel))
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#define SF_PWMCMPIP(_channel) (28 + (_channel))
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/* pwmcount scale factor */
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#define SF_PWMSCALEMASK 0xF
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#define SF_PWMSCALE(_val) (SF_PWMSCALEMASK & (_val))
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#define SF_PWMCOUNT_MIN_WIDTH 15
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/* Structure Declarations */
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struct pwm_sifive_data {};
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struct pwm_sifive_cfg {
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u32_t base;
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u32_t f_sys;
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u32_t cmpwidth;
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};
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/* Helper Functions */
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static inline void sys_set_mask(mem_addr_t addr, u32_t mask, u32_t value)
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{
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u32_t temp = sys_read32(addr);
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temp &= ~(mask);
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temp |= value;
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sys_write32(temp, addr);
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}
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/* API Functions */
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static int pwm_sifive_init(struct device *dev)
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{
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const struct pwm_sifive_cfg *config = dev->config->config_info;
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/* When pwms == pwmcmp0, reset the counter */
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sys_set_bit(PWM_REG(config, REG_PWMCFG), SF_PWMZEROCMP);
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/* Enable continuous operation */
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sys_set_bit(PWM_REG(config, REG_PWMCFG), SF_PWMENALWAYS);
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/* Clear IP config bits */
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sys_clear_bit(PWM_REG(config, REG_PWMCFG), SF_PWMSTICKY);
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sys_clear_bit(PWM_REG(config, REG_PWMCFG), SF_PWMDEGLITCH);
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/* Clear all channels */
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for (int i = 0; i < SF_NUMCHANNELS; i++) {
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/* Clear the channel comparator */
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sys_write32(0, PWM_REG(config, REG_PWMCMP(i)));
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/* Clear the compare center and compare gang bits */
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sys_clear_bit(PWM_REG(config, REG_PWMCFG), SF_PWMCMPCENTER(i));
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sys_clear_bit(PWM_REG(config, REG_PWMCFG), SF_PWMCMPGANG(i));
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}
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return 0;
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}
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static int pwm_sifive_pin_set(struct device *dev,
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u32_t pwm,
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u32_t period_cycles,
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u32_t pulse_cycles,
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pwm_flags_t flags)
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{
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const struct pwm_sifive_cfg *config = NULL;
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u32_t count_max = 0U;
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u32_t max_cmp_val = 0U;
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u32_t pwmscale = 0U;
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if (dev == NULL) {
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LOG_ERR("The device instance pointer was NULL\n");
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return -EFAULT;
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}
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if (dev->config == NULL) {
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LOG_ERR("The device config pointer was NULL\n");
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return -EFAULT;
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}
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if (flags) {
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/* PWM polarity not supported (yet?) */
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return -ENOTSUP;
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}
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config = dev->config->config_info;
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if (config == NULL) {
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LOG_ERR("The device configuration is NULL\n");
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return -EFAULT;
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}
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if (pwm >= SF_NUMCHANNELS) {
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LOG_ERR("The requested PWM channel %d is invalid\n", pwm);
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return -EINVAL;
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}
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/* Channel 0 sets the period, we can't output PWM with it */
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if ((pwm == 0U)) {
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LOG_ERR("PWM channel 0 cannot be configured\n");
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return -ENOTSUP;
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}
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/* We can't support periods greater than we can store in pwmcount */
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count_max = (1 << (config->cmpwidth + SF_PWMCOUNT_MIN_WIDTH)) - 1;
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if (period_cycles > count_max) {
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LOG_ERR("Requested period is %d but maximum is %d\n",
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period_cycles, count_max);
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return -EIO;
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}
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/* Calculate the maximum value that pwmcmpX can be set to */
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max_cmp_val = ((1 << config->cmpwidth) - 1);
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/*
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* Find the minimum value of pwmscale that will allow us to set the
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* requested period
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*/
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while ((period_cycles >> pwmscale) > max_cmp_val) {
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pwmscale++;
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}
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/* Make sure that we can scale that much */
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if (pwmscale > SF_PWMSCALEMASK) {
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LOG_ERR("Requested period is %d but maximum is %d\n",
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period_cycles, max_cmp_val << pwmscale);
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return -EIO;
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}
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if (pulse_cycles > period_cycles) {
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LOG_ERR("Requested pulse %d is longer than period %d\n",
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pulse_cycles, period_cycles);
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return -EIO;
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}
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/* Set the pwmscale field */
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sys_set_mask(PWM_REG(config, REG_PWMCFG),
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SF_PWMSCALEMASK,
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SF_PWMSCALE(pwmscale));
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/* Set the period by setting pwmcmp0 */
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sys_write32((period_cycles >> pwmscale), PWM_REG(config, REG_PWMCMP0));
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/* Set the duty cycle by setting pwmcmpX */
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sys_write32((pulse_cycles >> pwmscale),
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PWM_REG(config, REG_PWMCMP(pwm)));
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LOG_DBG("channel: %d, pwmscale: %d, pwmcmp0: %d, pwmcmp%d: %d",
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pwm,
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pwmscale,
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(period_cycles >> pwmscale),
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pwm,
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(pulse_cycles >> pwmscale));
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return 0;
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}
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static int pwm_sifive_get_cycles_per_sec(struct device *dev,
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u32_t pwm,
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u64_t *cycles)
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{
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const struct pwm_sifive_cfg *config;
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if (dev == NULL) {
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LOG_ERR("The device instance pointer was NULL\n");
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return -EFAULT;
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}
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if (dev->config == NULL) {
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LOG_ERR("The device config pointer was NULL\n");
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return -EFAULT;
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}
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config = dev->config->config_info;
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if (config == NULL) {
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LOG_ERR("The device configuration is NULL\n");
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return -EFAULT;
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}
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/* Fail if we don't have that channel */
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if (pwm >= SF_NUMCHANNELS) {
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return -EINVAL;
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}
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*cycles = config->f_sys;
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return 0;
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}
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/* Device Instantiation */
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static const struct pwm_driver_api pwm_sifive_api = {
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.pin_set = pwm_sifive_pin_set,
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.get_cycles_per_sec = pwm_sifive_get_cycles_per_sec,
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};
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#define PWM_SIFIVE_INIT(n) \
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static struct pwm_sifive_data pwm_sifive_data_##n; \
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static const struct pwm_sifive_cfg pwm_sifive_cfg_##n = { \
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.base = DT_INST_##n##_SIFIVE_PWM0_BASE_ADDRESS, \
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.f_sys = DT_INST_##n##_SIFIVE_PWM0_CLOCK_FREQUENCY, \
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.cmpwidth = DT_INST_##n##_SIFIVE_PWM0_SIFIVE_COMPARE_WIDTH, \
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}; \
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DEVICE_AND_API_INIT(pwm_##n, \
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DT_INST_##n##_SIFIVE_PWM0_LABEL, \
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pwm_sifive_init, \
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&pwm_sifive_data_##n, \
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&pwm_sifive_cfg_##n, \
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POST_KERNEL, \
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CONFIG_PWM_SIFIVE_INIT_PRIORITY, \
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&pwm_sifive_api)
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#ifdef DT_INST_0_SIFIVE_PWM0_LABEL
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PWM_SIFIVE_INIT(0);
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#endif /* DT_INST_0_SIFIVE_PWM0_LABEL */
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#ifdef DT_INST_1_SIFIVE_PWM0_LABEL
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PWM_SIFIVE_INIT(1);
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#endif /* DT_INST_1_SIFIVE_PWM0_LABEL */
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#ifdef DT_INST_2_SIFIVE_PWM0_LABEL
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PWM_SIFIVE_INIT(2);
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#endif /* DT_INST_2_SIFIVE_PWM0_LABEL */
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