410 lines
11 KiB
C
410 lines
11 KiB
C
/*
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* Copyright (c) 2016, Texas Instruments Incorporated
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <device.h>
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#include <drivers/gpio.h>
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#include <init.h>
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#include <kernel.h>
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#include <sys/sys_io.h>
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/* Driverlib includes */
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#include <inc/hw_types.h>
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#include <inc/hw_memmap.h>
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#include <inc/hw_ints.h>
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#include <inc/hw_gpio.h>
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#include <driverlib/rom.h>
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#include <driverlib/pin.h>
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#undef __GPIO_H__ /* Zephyr and CC32XX SDK gpio.h conflict */
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#include <driverlib/gpio.h>
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#include <driverlib/rom_map.h>
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#include <driverlib/interrupt.h>
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#include "gpio_utils.h"
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/* Reserved */
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#define PIN_XX 0xFF
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static const u8_t pinTable[] = {
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/* 00 01 02 03 04 05 06 07 */
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PIN_50, PIN_55, PIN_57, PIN_58, PIN_59, PIN_60, PIN_61, PIN_62,
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/* 08 09 10 11 12 13 14 15 */
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PIN_63, PIN_64, PIN_01, PIN_02, PIN_03, PIN_04, PIN_05, PIN_06,
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/* 16 17 18 19 20 21 22 23 */
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PIN_07, PIN_08, PIN_XX, PIN_XX, PIN_XX, PIN_XX, PIN_15, PIN_16,
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/* 24 25 26 27 28 29 30 31 */
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PIN_17, PIN_21, PIN_29, PIN_30, PIN_18, PIN_20, PIN_53, PIN_45,
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/* 32 */
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PIN_52
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};
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struct gpio_cc32xx_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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/* base address of GPIO port */
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unsigned long port_base;
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/* GPIO IRQ number */
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unsigned long irq_num;
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/* GPIO port number */
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u8_t port_num;
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};
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struct gpio_cc32xx_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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/* list of registered callbacks */
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sys_slist_t callbacks;
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/* callback enable pin bitmask */
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u32_t pin_callback_enables;
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};
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#define DEV_CFG(dev) \
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((const struct gpio_cc32xx_config *)(dev)->config->config_info)
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#define DEV_DATA(dev) \
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((struct gpio_cc32xx_data *)(dev)->driver_data)
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static int gpio_cc32xx_port_set_bits_raw(struct device *port, u32_t mask);
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static int gpio_cc32xx_port_clear_bits_raw(struct device *port, u32_t mask);
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static inline int gpio_cc32xx_config(struct device *port,
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gpio_pin_t pin,
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gpio_flags_t flags)
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{
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const struct gpio_cc32xx_config *gpio_config = DEV_CFG(port);
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unsigned long port_base = gpio_config->port_base;
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if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
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return -ENOTSUP;
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}
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if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == 0) {
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return -ENOTSUP;
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}
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if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
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return -ENOTSUP;
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}
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MAP_PinTypeGPIO(pinTable[gpio_config->port_num * 8 + pin],
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PIN_MODE_0, false);
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if (flags & GPIO_OUTPUT) {
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MAP_GPIODirModeSet(port_base, (1 << pin), GPIO_DIR_MODE_OUT);
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if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
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gpio_cc32xx_port_set_bits_raw(port, BIT(pin));
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} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
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gpio_cc32xx_port_clear_bits_raw(port, BIT(pin));
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}
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} else {
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MAP_GPIODirModeSet(port_base, (1 << pin), GPIO_DIR_MODE_IN);
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}
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return 0;
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}
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static int gpio_cc32xx_port_get_raw(struct device *port, u32_t *value)
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{
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const struct gpio_cc32xx_config *gpio_config = DEV_CFG(port);
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unsigned long port_base = gpio_config->port_base;
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unsigned char pin_packed = 0xFF;
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*value = MAP_GPIOPinRead(port_base, pin_packed);
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return 0;
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}
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static int gpio_cc32xx_port_set_masked_raw(struct device *port, u32_t mask,
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u32_t value)
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{
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const struct gpio_cc32xx_config *gpio_config = DEV_CFG(port);
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unsigned long port_base = gpio_config->port_base;
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MAP_GPIOPinWrite(port_base, (unsigned char)mask, (unsigned char)value);
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return 0;
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}
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static int gpio_cc32xx_port_set_bits_raw(struct device *port, u32_t mask)
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{
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const struct gpio_cc32xx_config *gpio_config = DEV_CFG(port);
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unsigned long port_base = gpio_config->port_base;
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MAP_GPIOPinWrite(port_base, (unsigned char)mask, (unsigned char)mask);
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return 0;
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}
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static int gpio_cc32xx_port_clear_bits_raw(struct device *port, u32_t mask)
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{
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const struct gpio_cc32xx_config *gpio_config = DEV_CFG(port);
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unsigned long port_base = gpio_config->port_base;
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MAP_GPIOPinWrite(port_base, (unsigned char)mask, (unsigned char)~mask);
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return 0;
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}
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static int gpio_cc32xx_port_toggle_bits(struct device *port, u32_t mask)
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{
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const struct gpio_cc32xx_config *gpio_config = DEV_CFG(port);
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unsigned long port_base = gpio_config->port_base;
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long value;
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value = MAP_GPIOPinRead(port_base, mask);
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MAP_GPIOPinWrite(port_base, (unsigned char)mask,
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(unsigned char)~value);
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return 0;
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}
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static int gpio_cc32xx_pin_interrupt_configure(struct device *port,
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gpio_pin_t pin, enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct gpio_cc32xx_config *gpio_config = DEV_CFG(port);
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struct gpio_cc32xx_data *data = DEV_DATA(port);
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unsigned long port_base = gpio_config->port_base;
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unsigned long int_type;
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__ASSERT(pin < 8, "Invalid pin number - only 8 pins per port");
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if (mode != GPIO_INT_MODE_DISABLED) {
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if (mode == GPIO_INT_MODE_EDGE) {
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if (trig == GPIO_INT_TRIG_BOTH) {
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int_type = GPIO_BOTH_EDGES;
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} else if (trig == GPIO_INT_TRIG_HIGH) {
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int_type = GPIO_RISING_EDGE;
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} else {
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int_type = GPIO_FALLING_EDGE;
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}
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} else { /* GPIO_INT_MODE_LEVEL */
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if (trig == GPIO_INT_TRIG_HIGH) {
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int_type = GPIO_HIGH_LEVEL;
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} else {
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int_type = GPIO_LOW_LEVEL;
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}
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}
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MAP_GPIOIntTypeSet(port_base, (1 << pin), int_type);
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MAP_GPIOIntClear(port_base, (1 << pin));
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MAP_GPIOIntEnable(port_base, (1 << pin));
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WRITE_BIT(data->pin_callback_enables, pin,
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mode != GPIO_INT_MODE_DISABLED);
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} else {
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MAP_GPIOIntDisable(port_base, (1 << pin));
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}
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return 0;
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}
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static int gpio_cc32xx_manage_callback(struct device *dev,
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struct gpio_callback *callback, bool set)
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{
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struct gpio_cc32xx_data *data = DEV_DATA(dev);
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return gpio_manage_callback(&data->callbacks, callback, set);
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}
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static int gpio_cc32xx_enable_callback(struct device *dev,
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gpio_pin_t pin)
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{
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struct gpio_cc32xx_data *data = DEV_DATA(dev);
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__ASSERT(pin < 8, "Invalid pin number - only 8 pins per port");
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data->pin_callback_enables |= (1 << pin);
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return 0;
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}
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static int gpio_cc32xx_disable_callback(struct device *dev,
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gpio_pin_t pin)
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{
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struct gpio_cc32xx_data *data = DEV_DATA(dev);
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__ASSERT(pin < 8, "Invalid pin number - only 8 pins per port");
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data->pin_callback_enables &= ~(1 << pin);
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return 0;
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}
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static void gpio_cc32xx_port_isr(void *arg)
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{
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struct device *dev = arg;
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const struct gpio_cc32xx_config *config = DEV_CFG(dev);
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struct gpio_cc32xx_data *data = DEV_DATA(dev);
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u32_t enabled_int, int_status;
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/* See which interrupts triggered: */
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int_status = (u32_t)MAP_GPIOIntStatus(config->port_base, 1);
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enabled_int = int_status & data->pin_callback_enables;
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/* Clear and Disable GPIO Interrupt */
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MAP_GPIOIntDisable(config->port_base, int_status);
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MAP_GPIOIntClear(config->port_base, int_status);
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/* Call the registered callbacks */
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gpio_fire_callbacks(&data->callbacks, (struct device *)dev,
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enabled_int);
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/* Re-enable the interrupts */
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MAP_GPIOIntEnable(config->port_base, int_status);
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}
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static const struct gpio_driver_api api_funcs = {
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.pin_configure = gpio_cc32xx_config,
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.port_get_raw = gpio_cc32xx_port_get_raw,
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.port_set_masked_raw = gpio_cc32xx_port_set_masked_raw,
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.port_set_bits_raw = gpio_cc32xx_port_set_bits_raw,
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.port_clear_bits_raw = gpio_cc32xx_port_clear_bits_raw,
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.port_toggle_bits = gpio_cc32xx_port_toggle_bits,
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.pin_interrupt_configure = gpio_cc32xx_pin_interrupt_configure,
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.manage_callback = gpio_cc32xx_manage_callback,
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.enable_callback = gpio_cc32xx_enable_callback,
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.disable_callback = gpio_cc32xx_disable_callback,
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};
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#ifdef CONFIG_GPIO_CC32XX_A0
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static const struct gpio_cc32xx_config gpio_cc32xx_a0_config = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_0_TI_CC32XX_GPIO_NGPIOS),
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},
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.port_base = DT_GPIO_CC32XX_A0_BASE_ADDRESS,
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.irq_num = DT_GPIO_CC32XX_A0_IRQ+16,
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.port_num = 0
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};
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static struct device DEVICE_NAME_GET(gpio_cc32xx_a0);
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static struct gpio_cc32xx_data gpio_cc32xx_a0_data;
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static int gpio_cc32xx_a0_init(struct device *dev)
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{
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ARG_UNUSED(dev);
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IRQ_CONNECT(DT_GPIO_CC32XX_A0_IRQ, DT_GPIO_CC32XX_A0_IRQ_PRI,
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gpio_cc32xx_port_isr, DEVICE_GET(gpio_cc32xx_a0), 0);
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MAP_IntPendClear(DT_GPIO_CC32XX_A0_IRQ+16);
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irq_enable(DT_GPIO_CC32XX_A0_IRQ);
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return 0;
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}
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DEVICE_AND_API_INIT(gpio_cc32xx_a0, DT_GPIO_CC32XX_A0_NAME,
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&gpio_cc32xx_a0_init, &gpio_cc32xx_a0_data,
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&gpio_cc32xx_a0_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&api_funcs);
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#endif
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#ifdef CONFIG_GPIO_CC32XX_A1
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static const struct gpio_cc32xx_config gpio_cc32xx_a1_config = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_1_TI_CC32XX_GPIO_NGPIOS),
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},
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.port_base = DT_GPIO_CC32XX_A1_BASE_ADDRESS,
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.irq_num = DT_GPIO_CC32XX_A1_IRQ+16,
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.port_num = 1
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};
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static struct device DEVICE_NAME_GET(gpio_cc32xx_a1);
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static struct gpio_cc32xx_data gpio_cc32xx_a1_data;
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static int gpio_cc32xx_a1_init(struct device *dev)
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{
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ARG_UNUSED(dev);
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IRQ_CONNECT(DT_GPIO_CC32XX_A1_IRQ, DT_GPIO_CC32XX_A1_IRQ_PRI,
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gpio_cc32xx_port_isr, DEVICE_GET(gpio_cc32xx_a1), 0);
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MAP_IntPendClear(DT_GPIO_CC32XX_A1_IRQ+16);
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irq_enable(DT_GPIO_CC32XX_A1_IRQ);
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return 0;
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}
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DEVICE_AND_API_INIT(gpio_cc32xx_a1, DT_GPIO_CC32XX_A1_NAME,
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&gpio_cc32xx_a1_init, &gpio_cc32xx_a1_data,
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&gpio_cc32xx_a1_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&api_funcs);
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#endif /* CONFIG_GPIO_CC32XX_A1 */
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#ifdef CONFIG_GPIO_CC32XX_A2
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static const struct gpio_cc32xx_config gpio_cc32xx_a2_config = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_2_TI_CC32XX_GPIO_NGPIOS),
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},
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.port_base = DT_GPIO_CC32XX_A2_BASE_ADDRESS,
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.irq_num = DT_GPIO_CC32XX_A2_IRQ+16,
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.port_num = 2
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};
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static struct device DEVICE_NAME_GET(gpio_cc32xx_a2);
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static struct gpio_cc32xx_data gpio_cc32xx_a2_data;
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static int gpio_cc32xx_a2_init(struct device *dev)
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{
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ARG_UNUSED(dev);
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IRQ_CONNECT(DT_GPIO_CC32XX_A2_IRQ, DT_GPIO_CC32XX_A2_IRQ_PRI,
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gpio_cc32xx_port_isr, DEVICE_GET(gpio_cc32xx_a2), 0);
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MAP_IntPendClear(DT_GPIO_CC32XX_A2_IRQ+16);
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irq_enable(DT_GPIO_CC32XX_A2_IRQ);
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return 0;
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}
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DEVICE_AND_API_INIT(gpio_cc32xx_a2, DT_GPIO_CC32XX_A2_NAME,
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&gpio_cc32xx_a2_init, &gpio_cc32xx_a2_data,
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&gpio_cc32xx_a2_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&api_funcs);
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#endif
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#ifdef CONFIG_GPIO_CC32XX_A3
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static const struct gpio_cc32xx_config gpio_cc32xx_a3_config = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_3_TI_CC32XX_GPIO_NGPIOS),
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},
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.port_base = DT_GPIO_CC32XX_A3_BASE_ADDRESS,
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.irq_num = DT_GPIO_CC32XX_A3_IRQ+16,
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.port_num = 3
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};
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static struct device DEVICE_NAME_GET(gpio_cc32xx_a3);
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static struct gpio_cc32xx_data gpio_cc32xx_a3_data;
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static int gpio_cc32xx_a3_init(struct device *dev)
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{
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ARG_UNUSED(dev);
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IRQ_CONNECT(DT_GPIO_CC32XX_A3_IRQ, DT_GPIO_CC32XX_A3_IRQ_PRI,
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gpio_cc32xx_port_isr, DEVICE_GET(gpio_cc32xx_a3), 0);
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MAP_IntPendClear(DT_GPIO_CC32XX_A3_IRQ+16);
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irq_enable(DT_GPIO_CC32XX_A3_IRQ);
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return 0;
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}
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DEVICE_AND_API_INIT(gpio_cc32xx_a3, DT_GPIO_CC32XX_A3_NAME,
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&gpio_cc32xx_a3_init, &gpio_cc32xx_a3_data,
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&gpio_cc32xx_a3_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&api_funcs);
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#endif
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