128 lines
3.3 KiB
C
128 lines
3.3 KiB
C
/*
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* Copyright (c) 2016 Linaro Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Driver to provide the GPIO API for a simple 32-bit i/o register
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*
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* This is a driver for accessing a simple, fixed purpose, 32-bit
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* memory-mapped i/o register using the same APIs as GPIO drivers. This is
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* useful when an SoC or board has registers that aren't part of a GPIO IP
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* block and these registers are used to control things that Zephyr normally
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* expects to be specified using a GPIO pin, e.g. for driving an LED, or
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* chip-select line for an SPI device.
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*
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* The implementation expects that all bits of the hardware register are both
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* readable and writable, and that for any bits that act as outputs, the value
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* read will have the value that was last written to it. This requirement
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* stems from the use of a read-modify-write method for all changes.
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*
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* It is possible to specify a restricted mask of bits that are valid for
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* access, and whenever the register is written, the value of bits outside this
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* mask will be preserved, even when the whole port is written to using
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* gpio_port_write.
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*/
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#include <gpio/gpio_mmio32.h>
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#include <errno.h>
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static int gpio_mmio32_config(struct device *dev, int access_op,
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u32_t pin, int flags)
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{
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struct gpio_mmio32_context *context = dev->driver_data;
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const struct gpio_mmio32_config *config = context->config;
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if (flags & GPIO_INT) {
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return -ENOTSUP;
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}
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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if ((config->mask & (1 << pin)) == 0) {
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return -EINVAL; /* Pin not in our validity mask */
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}
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if (flags & ~(GPIO_DIR_MASK | GPIO_POL_MASK)) {
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/* We ignore direction and fake polarity, rest is unsupported */
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return -ENOTSUP;
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}
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if ((flags & GPIO_POL_MASK) == GPIO_POL_INV) {
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context->invert |= (1 << pin);
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} else {
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context->invert &= ~(1 << pin);
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}
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return 0;
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}
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static int gpio_mmio32_write(struct device *dev, int access_op,
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u32_t pin, u32_t value)
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{
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struct gpio_mmio32_context *context = dev->driver_data;
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const struct gpio_mmio32_config *config = context->config;
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volatile u32_t *reg = config->reg;
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u32_t mask = config->mask;
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u32_t invert = context->invert;
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unsigned int key;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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mask &= 1 << pin;
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if (!mask) {
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return -EINVAL; /* Pin not in our validity mask */
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}
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value = value ? mask : 0;
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}
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value = (value ^ invert) & mask;
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/* Update pin state atomically */
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key = irq_lock();
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*reg = (*reg & ~mask) | value;
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irq_unlock(key);
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return 0;
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}
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static int gpio_mmio32_read(struct device *dev, int access_op,
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u32_t pin, u32_t *value)
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{
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struct gpio_mmio32_context *context = dev->driver_data;
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const struct gpio_mmio32_config *config = context->config;
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u32_t bits;
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bits = (*config->reg ^ context->invert) & config->mask;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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*value = (bits >> pin) & 1;
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if ((config->mask & (1 << pin)) == 0) {
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return -EINVAL; /* Pin not in our validity mask */
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}
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} else {
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*value = bits;
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}
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return 0;
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}
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static const struct gpio_driver_api gpio_mmio32_api = {
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.config = gpio_mmio32_config,
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.write = gpio_mmio32_write,
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.read = gpio_mmio32_read,
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};
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int gpio_mmio32_init(struct device *dev)
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{
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struct gpio_mmio32_context *context = dev->driver_data;
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const struct gpio_mmio32_config *config = dev->config->config_info;
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context->config = config;
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dev->driver_api = &gpio_mmio32_api;
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return 0;
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}
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