460 lines
11 KiB
C
460 lines
11 KiB
C
/*
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* Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <drivers/counter.h>
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#include <device.h>
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#include <soc.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(counter_sam0_tc32, CONFIG_COUNTER_LOG_LEVEL);
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struct counter_sam0_tc32_ch_data {
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counter_alarm_callback_t callback;
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void *user_data;
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};
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struct counter_sam0_tc32_data {
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counter_top_callback_t top_cb;
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void *top_user_data;
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struct counter_sam0_tc32_ch_data ch;
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};
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struct counter_sam0_tc32_config {
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struct counter_config_info info;
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TcCount32 *regs;
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#ifdef MCLK
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volatile u32_t *mclk;
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u32_t mclk_mask;
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u16_t gclk_id;
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#else
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u32_t pm_apbcmask;
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u16_t gclk_clkctrl_id;
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#endif
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u16_t prescaler;
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void (*irq_config_func)(struct device *dev);
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};
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#define DEV_CFG(dev) ((const struct counter_sam0_tc32_config *const) \
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(dev)->config->config_info)
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#define DEV_DATA(dev) ((struct counter_sam0_tc32_data *const) \
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(dev)->driver_data)
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static void wait_synchronization(TcCount32 *regs)
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{
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#if defined(TC_SYNCBUSY_MASK)
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/* SYNCBUSY is a register */
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while ((regs->SYNCBUSY.reg & TC_SYNCBUSY_MASK) != 0) {
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}
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#elif defined(TC_STATUS_SYNCBUSY)
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/* SYNCBUSY is a bit */
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while ((regs->STATUS.reg & TC_STATUS_SYNCBUSY) != 0) {
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}
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#else
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#error Unsupported device
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#endif
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}
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static void read_synchronize_count(TcCount32 *regs)
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{
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#if defined(TC_READREQ_RREQ)
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regs->READREQ.reg = TC_READREQ_RREQ |
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TC_READREQ_ADDR(TC_COUNT32_COUNT_OFFSET);
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wait_synchronization(regs);
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#elif defined(TC_CTRLBSET_CMD_READSYNC)
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regs->CTRLBSET.reg = TC_CTRLBSET_CMD_READSYNC;
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wait_synchronization(regs);
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#else
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ARG_UNUSED(regs);
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#endif
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}
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static int counter_sam0_tc32_start(struct device *dev)
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{
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const struct counter_sam0_tc32_config *const cfg = DEV_CFG(dev);
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TcCount32 *tc = cfg->regs;
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/*
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* This will also reset the current counter value if it's
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* already running.
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*/
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tc->CTRLBSET.reg = TC_CTRLBSET_CMD_RETRIGGER;
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wait_synchronization(tc);
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return 0;
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}
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static int counter_sam0_tc32_stop(struct device *dev)
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{
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const struct counter_sam0_tc32_config *const cfg = DEV_CFG(dev);
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TcCount32 *tc = cfg->regs;
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/*
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* The older (pre SAML1x) manuals claim the counter retains its
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* value on stop, but this doesn't actually seem to happen.
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* The SAML1x manual says it resets, which is what the SAMD21
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* counter actually appears to do.
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*/
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tc->CTRLBSET.reg = TC_CTRLBSET_CMD_STOP;
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wait_synchronization(tc);
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return 0;
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}
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static u32_t counter_sam0_tc32_read(struct device *dev)
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{
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const struct counter_sam0_tc32_config *const cfg = DEV_CFG(dev);
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TcCount32 *tc = cfg->regs;
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read_synchronize_count(tc);
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return tc->COUNT.reg;
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}
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static void counter_sam0_tc32_relative_alarm(struct device *dev, u32_t ticks)
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{
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struct counter_sam0_tc32_data *data = DEV_DATA(dev);
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const struct counter_sam0_tc32_config *const cfg = DEV_CFG(dev);
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TcCount32 *tc = cfg->regs;
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u32_t before;
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u32_t target;
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u32_t after;
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u32_t max;
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read_synchronize_count(tc);
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before = tc->COUNT.reg;
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target = before + ticks;
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max = tc->CC[0].reg;
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if (target > max) {
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target -= max;
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}
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tc->CC[1].reg = target;
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wait_synchronization(tc);
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tc->INTFLAG.reg = TC_INTFLAG_MC1;
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read_synchronize_count(tc);
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after = tc->COUNT.reg;
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/* Pending now, so no further checking required */
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if (tc->INTFLAG.bit.MC1) {
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goto out_future;
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}
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/*
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* Check if we missed the interrupt and call the handler
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* immediately if we did.
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*/
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if (after < target) {
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goto out_future;
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}
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/* Check wrapped */
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if (target < before && after >= before) {
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goto out_future;
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}
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counter_alarm_callback_t cb = data->ch.callback;
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tc->INTENCLR.reg = TC_INTENCLR_MC1;
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tc->INTFLAG.reg = TC_INTFLAG_MC1;
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data->ch.callback = NULL;
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cb(dev, 0, target, data->ch.user_data);
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return;
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out_future:
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tc->INTENSET.reg = TC_INTFLAG_MC1;
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}
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static int counter_sam0_tc32_set_alarm(struct device *dev, u8_t chan_id,
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const struct counter_alarm_cfg *alarm_cfg)
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{
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struct counter_sam0_tc32_data *data = DEV_DATA(dev);
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const struct counter_sam0_tc32_config *const cfg = DEV_CFG(dev);
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TcCount32 *tc = cfg->regs;
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ARG_UNUSED(chan_id);
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if (alarm_cfg->ticks > tc->CC[0].reg) {
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return -EINVAL;
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}
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int key = irq_lock();
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if (data->ch.callback) {
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irq_unlock(key);
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return -EBUSY;
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}
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data->ch.callback = alarm_cfg->callback;
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data->ch.user_data = alarm_cfg->user_data;
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if ((alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) != 0) {
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tc->CC[1].reg = alarm_cfg->ticks;
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wait_synchronization(tc);
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tc->INTFLAG.reg = TC_INTFLAG_MC1;
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tc->INTENSET.reg = TC_INTFLAG_MC1;
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} else {
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counter_sam0_tc32_relative_alarm(dev, alarm_cfg->ticks);
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}
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irq_unlock(key);
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return 0;
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}
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static int counter_sam0_tc32_cancel_alarm(struct device *dev, u8_t chan_id)
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{
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struct counter_sam0_tc32_data *data = DEV_DATA(dev);
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const struct counter_sam0_tc32_config *const cfg = DEV_CFG(dev);
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TcCount32 *tc = cfg->regs;
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int key = irq_lock();
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ARG_UNUSED(chan_id);
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data->ch.callback = NULL;
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tc->INTENCLR.reg = TC_INTENCLR_MC1;
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tc->INTFLAG.reg = TC_INTFLAG_MC1;
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irq_unlock(key);
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return 0;
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}
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static int counter_sam0_tc32_set_top_value(struct device *dev,
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const struct counter_top_cfg *top_cfg)
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{
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struct counter_sam0_tc32_data *data = DEV_DATA(dev);
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const struct counter_sam0_tc32_config *const cfg = DEV_CFG(dev);
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TcCount32 *tc = cfg->regs;
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int err = 0;
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int key = irq_lock();
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if (data->ch.callback) {
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irq_unlock(key);
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return -EBUSY;
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}
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if (top_cfg->callback) {
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data->top_cb = top_cfg->callback;
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data->top_user_data = top_cfg->user_data;
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tc->INTENSET.reg = TC_INTFLAG_MC0;
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} else {
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tc->INTENCLR.reg = TC_INTFLAG_MC0;
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}
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tc->CC[0].reg = top_cfg->ticks;
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if (top_cfg->flags & COUNTER_TOP_CFG_DONT_RESET) {
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/*
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* Top trigger is on equality of the rising edge only, so
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* manually reset it if the counter has missed the new top.
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*/
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if (counter_sam0_tc32_read(dev) >= top_cfg->ticks) {
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err = -ETIME;
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if (top_cfg->flags & COUNTER_TOP_CFG_RESET_WHEN_LATE) {
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tc->CTRLBSET.reg = TC_CTRLBSET_CMD_RETRIGGER;
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}
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}
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} else {
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tc->CTRLBSET.reg = TC_CTRLBSET_CMD_RETRIGGER;
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}
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wait_synchronization(tc);
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tc->INTFLAG.reg = TC_INTFLAG_MC0;
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irq_unlock(key);
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return err;
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}
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static u32_t counter_sam0_tc32_get_pending_int(struct device *dev)
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{
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const struct counter_sam0_tc32_config *const cfg = DEV_CFG(dev);
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TcCount32 *tc = cfg->regs;
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return tc->INTFLAG.reg & (TC_INTFLAG_MC0 | TC_INTFLAG_MC1);
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}
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static u32_t counter_sam0_tc32_get_top_value(struct device *dev)
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{
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const struct counter_sam0_tc32_config *const cfg = DEV_CFG(dev);
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TcCount32 *tc = cfg->regs;
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/*
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* Unsync read is safe here because we're not using
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* capture mode, so things are only set from the CPU
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* end.
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*/
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return tc->CC[0].reg;
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}
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static u32_t counter_sam0_tc32_get_max_relative_alarm(struct device *dev)
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{
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return counter_sam0_tc32_get_top_value(dev) - 1;
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}
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static void counter_sam0_tc32_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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struct counter_sam0_tc32_data *data = DEV_DATA(dev);
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const struct counter_sam0_tc32_config *const cfg = DEV_CFG(dev);
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TcCount32 *tc = cfg->regs;
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u8_t status = tc->INTFLAG.reg;
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/* Acknowledge all interrupts */
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tc->INTFLAG.reg = status;
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if (status & TC_INTFLAG_MC1) {
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if (data->ch.callback) {
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counter_alarm_callback_t cb = data->ch.callback;
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tc->INTENCLR.reg = TC_INTENCLR_MC1;
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data->ch.callback = NULL;
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cb(dev, 0, tc->CC[1].reg, data->ch.user_data);
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}
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}
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if (status & TC_INTFLAG_MC0) {
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if (data->top_cb) {
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data->top_cb(dev, data->top_user_data);
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}
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}
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}
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static int counter_sam0_tc32_initialize(struct device *dev)
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{
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const struct counter_sam0_tc32_config *const cfg = DEV_CFG(dev);
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TcCount32 *tc = cfg->regs;
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#ifdef MCLK
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/* Enable the GCLK */
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GCLK->PCHCTRL[cfg->gclk_id].reg = GCLK_PCHCTRL_GEN_GCLK0 |
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GCLK_PCHCTRL_CHEN;
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/* Enable TC clock in MCLK */
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*cfg->mclk |= cfg->mclk_mask;
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#else
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/* Enable the GCLK */
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GCLK->CLKCTRL.reg = cfg->gclk_clkctrl_id | GCLK_CLKCTRL_GEN_GCLK0 |
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GCLK_CLKCTRL_CLKEN;
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/* Enable clock in PM */
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PM->APBCMASK.reg |= cfg->pm_apbcmask;
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#endif
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/*
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* In 32 bit mode, NFRQ mode always uses MAX as the counter top, so
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* use MFRQ mode which uses CC0 as the top at the expense of only
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* having CC1 available for alarms.
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*/
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tc->CTRLA.reg = TC_CTRLA_MODE_COUNT32 |
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#ifdef TC_CTRLA_WAVEGEN_MFRQ
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TC_CTRLA_WAVEGEN_MFRQ |
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#endif
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cfg->prescaler;
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wait_synchronization(tc);
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#ifdef TC_WAVE_WAVEGEN_MFRQ
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tc->WAVE.reg = TC_WAVE_WAVEGEN_MFRQ;
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#endif
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/* Disable all interrupts */
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tc->INTENCLR.reg = TC_INTENCLR_MASK;
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/* Set the initial top as the maximum */
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tc->CC[0].reg = UINT32_MAX;
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cfg->irq_config_func(dev);
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tc->CTRLA.bit.ENABLE = 1;
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wait_synchronization(tc);
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/* Stop the counter initially */
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tc->CTRLBSET.reg = TC_CTRLBSET_CMD_STOP;
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wait_synchronization(tc);
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return 0;
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}
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static const struct counter_driver_api counter_sam0_tc32_driver_api = {
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.start = counter_sam0_tc32_start,
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.stop = counter_sam0_tc32_stop,
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.read = counter_sam0_tc32_read,
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.set_alarm = counter_sam0_tc32_set_alarm,
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.cancel_alarm = counter_sam0_tc32_cancel_alarm,
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.set_top_value = counter_sam0_tc32_set_top_value,
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.get_pending_int = counter_sam0_tc32_get_pending_int,
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.get_top_value = counter_sam0_tc32_get_top_value,
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.get_max_relative_alarm = counter_sam0_tc32_get_max_relative_alarm,
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};
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#ifdef MCLK
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#define COUNTER_SAM0_TC32_CLOCK_CONTROL(n) \
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.mclk = MCLK_TC##n, \
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.mclk_mask = MCLK_TC##n##_MASK, \
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.gclk_id = TC##n##_GCLK_ID,
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#else
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#define COUNTER_SAM0_TC32_CLOCK_CONTROL(n) \
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.pm_apbcmask = PM_APBCMASK_TC##n, \
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.gclk_clkctrl_id = UTIL_CAT(GCLK_CLKCTRL_ID_TC ## n ## _TC, \
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UTIL_INC(n)),
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#endif
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#define COUNTER_SAM0_TC32_DEVICE(n) \
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static void counter_sam0_tc32_config_##n(struct device *dev); \
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static const struct counter_sam0_tc32_config \
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counter_sam0_tc32_dev_config_##n = { \
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.info = { \
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.max_top_value = UINT32_MAX, \
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.freq = SOC_ATMEL_SAM0_GCLK0_FREQ_HZ / \
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CONFIG_COUNTER_SAM0_TC32_##n##_DIVISOR, \
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.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
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.channels = 1 \
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}, \
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.regs = (TcCount32 *)DT_ATMEL_SAM0_TC32_TC_##n##_BASE_ADDRESS,\
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COUNTER_SAM0_TC32_CLOCK_CONTROL(n) \
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.prescaler = UTIL_CAT(TC_CTRLA_PRESCALER_DIV, \
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CONFIG_COUNTER_SAM0_TC32_##n##_DIVISOR), \
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.irq_config_func = &counter_sam0_tc32_config_##n, \
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}; \
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static struct counter_sam0_tc32_data counter_sam0_tc32_dev_data_##n; \
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DEVICE_AND_API_INIT(counter_sam0_tc32_##n, \
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DT_ATMEL_SAM0_TC32_TC_##n##_LABEL, \
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&counter_sam0_tc32_initialize, \
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&counter_sam0_tc32_dev_data_##n, \
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&counter_sam0_tc32_dev_config_##n, PRE_KERNEL_1, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&counter_sam0_tc32_driver_api); \
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static void counter_sam0_tc32_config_##n(struct device *dev) \
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{ \
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IRQ_CONNECT(DT_ATMEL_SAM0_TC32_TC_##n##_IRQ_0, \
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DT_ATMEL_SAM0_TC32_TC_##n##_IRQ_0_PRIORITY, \
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counter_sam0_tc32_isr, \
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DEVICE_GET(counter_sam0_tc32_##n), \
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0); \
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irq_enable(DT_ATMEL_SAM0_TC32_TC_##n##_IRQ_0); \
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}
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#if DT_ATMEL_SAM0_TC32_TC_0_BASE_ADDRESS
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COUNTER_SAM0_TC32_DEVICE(0);
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#endif
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#if DT_ATMEL_SAM0_TC32_TC_2_BASE_ADDRESS
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COUNTER_SAM0_TC32_DEVICE(2);
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#endif
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#if DT_ATMEL_SAM0_TC32_TC_4_BASE_ADDRESS
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COUNTER_SAM0_TC32_DEVICE(4);
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#endif
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#if DT_ATMEL_SAM0_TC32_TC_6_BASE_ADDRESS
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COUNTER_SAM0_TC32_DEVICE(6);
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#endif
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