zephyr/arch/xtensa/soc/sample_controller/include
Andy Ross 7de010b5e5 xtensa: Interrupt generator script and output for qemu & esp32
This python script reads the core-isa.h interrupt definitions (via
running a template file through the toolchain preprocessor to generate
an input file) and emits a fully populated, optimized C handling code
that binary searches only the declared interrupts at a given level and
correctly detects spurious interrupts (and/or incorrect core-isa.h
definitions).

The generated code, alas, turns out not to be any faster than simply
searching the interrupt mask with CLZ (er, NSAU in xtensese), though
it could be faster in theory if the compiler made different choices,
see comments.  But I like this for the robustness of the fully
populated search trees and the checking of level vs. mask.

This simply commits the script output into the source tree, including
some checking code to force a build error if the toolchain changes the
headers incompatibly.  It would be better long term to have these
headers be generated at build time, but that requires more cmake fu
than I have.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
..
_soc_inthandlers.h