197 lines
7.2 KiB
YAML
197 lines
7.2 KiB
YAML
# Copyright (c) 2022 Georgij Cernysiov
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# SPDX-License-Identifier: Apache-2.0
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description: |
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STM32 Flexible Memory Controller (NOR Flash/PSRAM/SRAM controller).
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The FMC generates the appropriate signal timings to drive the
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following types of memories:
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* Asynchronous SRAM and ROM
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- 8 bits
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- 16 bits
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- 32 bits
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* PSRAM (Cellular RAM)
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- Asynchronous mode
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- Burst mode for synchronous accesses with configurable option to split burst
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access when crossing boundary page for CRAM 1.5.
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- Multiplexed or non-multiplexed
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* NOR Flash memory
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- Asynchronous mode
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- Burst mode for synchronous accesses
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- Multiplexed or non-multiplexed
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A unique Chip Select signal (NE) is used per bank. All the other
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signals (addresses, data and control) are shared. A wide range of
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devices is supported through programmable timings.
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Refer to the reference manual for more details.
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The FMC NOR/PSRAM controller is defined below the FMC node and banks are
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defined as child nodes of the FMC NOR/PSRAM controller node.
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You can enable the controller in devicetree as follows:
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&fmc {
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status = "okay";
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pinctrl-0 = <&fmc_nwe_pd5 &fmc_noe_pd4 ...>;
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pinctrl-names = "default";
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sram {
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status = "okay";
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compatible = "st,stm32-fmc-nor-psram";
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#address-cells = <1>;
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#size-cells = <0>;
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sram2@2 {
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reg = <0x2>;
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st,control = <STM32_FMC_DATA_ADDRESS_MUX_DISABLE
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STM32_FMC_MEMORY_TYPE_SRAM
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STM32_FMC_NORSRAM_MEM_BUS_WIDTH_16
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STM32_FMC_BURST_ACCESS_MODE_DISABLE
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STM32_FMC_WAIT_SIGNAL_POLARITY_LOW
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STM32_FMC_WAIT_TIMING_BEFORE_WS
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STM32_FMC_WRITE_OPERATION_ENABLE
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STM32_FMC_WAIT_SIGNAL_DISABLE
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STM32_FMC_EXTENDED_MODE_DISABLE
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STM32_FMC_ASYNCHRONOUS_WAIT_DISABLE
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STM32_FMC_WRITE_BURST_DISABLE
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STM32_FMC_CONTINUOUS_CLOCK_SYNC_ONLY
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STM32_FMC_WRITE_FIFO_DISABLE
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STM32_FMC_PAGE_SIZE_NONE>;
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st,timing = <4 2 3 0 16 17 STM32_FMC_ACCESS_MODE_A>;
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};
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};
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};
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Use constants defined in dt-bindings/memory-controller/stm32-fmc-nor-psram.h.
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compatible: "st,stm32-fmc-nor-psram"
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include: base.yaml
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properties:
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"#address-cells":
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required: true
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const: 1
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"#size-cells":
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required: true
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const: 0
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child-binding:
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description: NOR/PSRAM bank.
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properties:
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reg:
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type: int
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required: true
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st,control:
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type: array
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required: true
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description: |
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SRAM/NOR-Flash control register (FMC_BCRx).
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Contains control information of each memory bank,
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used for SRAMs, PSRAM and NOR Flash memories.
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Expected fields, in order:
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* MUXEN - Address/data multiplexing enable bit.
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* MTYP - Memory type.
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* MWID - Memory data bus width.
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* FACCEN - Flash access enable.
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* BURSTEN - Burst enable bit.
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* WAITPOL - Wait signal polarity bit.
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* WAITCFG - Wait timing configuration.
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* WREN - Write enable bit.
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* WAITEN - Wait enable bit.
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* EXTMOD - Extended mode enable.
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If set, then 'st,timing-ext' shall be provided.
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* ASYNCWAIT - Wait signal during asynchronous transfers.
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* CPSIZE - Cellular RAM (CRAM) 1.5 Page Size.
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* CBURSTRW - Write burst enable.
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* CCLKEN - Continuous Clock Enable.
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* WFDIS - Write FIFO Disable.
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* BMAP - FMC bank mapping.
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st,timing:
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type: array
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required: true
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description: |
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SRAM/NOR-Flash (read) timing register (FMC_BTRx).
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If the EXTMOD is set (see control register FMC_BCRx), then
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FMC_BTRx register is partitioned for write and read access.
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That means, use this property to configure read accesses and
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'st,timing-ext' to configure write accesses.
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Expected fields, in order:
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* ADDSET - Address setup phase duration.
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Number of HCLK cycles to configure the duration of
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the address setup time. This parameter can be a value
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between Min_Data = 0 and Max_Data = 15.
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Note: Not used with synchronous NOR Flash memories.
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* ADDHLD - Address-hold phase duration.
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Number of HCLK cycles to configure the duration of
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the address hold time. This parameter can be a value
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between Min_Data = 1 and Max_Data = 15.
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Note: Not used with synchronous NOR Flash memories.
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* DATAST - Data-phase duration.
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Number of HCLK cycles to configure the duration of
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the data setup time. This parameter can be a value
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between Min_Data = 1 and Max_Data = 255.
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Note: Used for SRAMs, ROMs and asynchronous multiplexed
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NOR Flash memories.
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* BUSTURN - Bus turnaround phase duration.
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Number of HCLK cycles to configure the duration of
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the bus turnaround. This parameter can be a value
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between Min_Data = 0 and Max_Data = 15.
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Note: Only used for multiplexed NOR Flash memories.
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* CLKDIV - Clock divide ratio (for FMC_CLK signal).
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Period of CLK clock output signal, expressed in number of
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HCLK cycles. This parameter can be a value
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between Min_Data = 2 and Max_Data = 16.
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Note: Not used for asynchronous NOR Flash, SRAM or ROM
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accesses.
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* DATLAT - Data latency for synchronous memory.
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Number of memory clock cycles to issue to the memory
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before getting the first data.
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The value depends on the memory type as shown below:
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- It must be set to 0 in case of a CRAM
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- It is don't care in asynchronous NOR, SRAM or ROM accesses
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- It may assume a value between Min_Data = 2 and Max_Data = 17
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in NOR Flash memories with synchronous burst mode enable
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* ACCMOD - Access mode.
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See access mode defines
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in dt-bindings/memory-controller/stm32-fmc-nor-psram.h.
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st,timing-ext:
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type: array
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default: [0xF, 0xF, 0xFF, 0xF, 0x0] # reset state
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description: |
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SRAM/NOR-Flash (write) timing register (FMC_BWTRx).
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Expected fields, in order:
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* ADDSET - Address setup phase duration.
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Reset state: 15 (0xF).
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* ADDHLD - Address-hold phase duration.
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Reset state: 15 (0xF).
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* DATAST - Data-phase duration.
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Reset state: 255 (0xFF).
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* BUSTURN - Bus turnaround phase duration.
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Reset state: 15 (0xF).
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* ACCMOD - Access mode.
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Reset state: 0 (0x0).
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Refer to 'st,timing' for detailed field descriptions.
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This property is applied only when EXTMOD is set
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(see control register FMC_BCRx).
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If absent, then reset state values are used.
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