400 lines
8.5 KiB
ArmAsm
400 lines
8.5 KiB
ArmAsm
/*
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* Copyright (c) 2022, Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <xtensa_asm2_s.h>
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#include <offsets.h>
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#include <offsets_short.h>
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#include <zephyr/syscall.h>
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#include <zsr.h>
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#include <xtensa/config/core-isa.h>
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/**
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* syscall number arg1, arg2, arg3, arg4, arg5, arg6
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* -------------- ----------------------------------
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* a2 a6, a3, a4, a5, a8, a9
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*
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**/
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.pushsection .text.xtensa_do_syscall, "ax"
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.global xtensa_do_syscall
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.align 4
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xtensa_do_syscall:
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#if XCHAL_HAVE_THREADPTR == 0
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wsr a2, ZSR_SYSCALL_SCRATCH
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rsync
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movi a0, xtensa_is_user_context_epc
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rsr.epc1 a2
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bne a0, a2, _not_checking_user_context
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addi a2, a2, 3
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wsr.epc1 a2
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movi a0, PS_RING_MASK
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rsr.ps a2
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and a2, a2, a0
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/* Need to set return to 1 if RING != 0,
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* so we won't be leaking which ring we are in
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* right now.
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*/
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beqz a2, _is_user_context_return
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movi a2, 1
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_is_user_context_return:
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rsr a0, ZSR_A0SAVE
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rfe
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_not_checking_user_context:
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rsr a2, ZSR_SYSCALL_SCRATCH
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#endif
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rsr a0, ZSR_CPU
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l32i a0, a0, ___cpu_t_current_OFFSET
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l32i a0, a0, _thread_offset_to_psp
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addi a0, a0, -___xtensa_irq_bsa_t_SIZEOF
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s32i a1, a0, ___xtensa_irq_bsa_t_scratch_OFFSET
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s32i a2, a0, ___xtensa_irq_bsa_t_a2_OFFSET
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s32i a3, a0, ___xtensa_irq_bsa_t_a3_OFFSET
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rsr a2, ZSR_A0SAVE
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s32i a2, a0, ___xtensa_irq_bsa_t_a0_OFFSET
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rsr.ps a2
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movi a3, ~PS_OWB_MASK
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and a2, a2, a3
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s32i a2, a0, ___xtensa_irq_bsa_t_ps_OFFSET
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rsr.epc1 a2
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s32i a2, a0, ___xtensa_irq_bsa_t_pc_OFFSET
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#if XCHAL_HAVE_NMI
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movi a2, PS_WOE|PS_INTLEVEL(XCHAL_NMILEVEL)
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#elif XCHAL_HAVE_INTERRUPTS
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movi a2, PS_WOE|PS_INTLEVEL(XCHAL_NUM_INTLEVELS)
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#else
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#error Xtensa core with no interrupt support is used
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#endif
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rsr.ps a3
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or a3, a3, a2
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movi a2, ~(PS_EXCM | PS_RING_MASK)
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and a3, a3, a2
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wsr.ps a3
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rsync
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l32i a2, a0, ___xtensa_irq_bsa_t_a2_OFFSET
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l32i a3, a0, ___xtensa_irq_bsa_t_a3_OFFSET
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SPILL_ALL_WINDOWS
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rsr a0, ZSR_CPU
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l32i a0, a0, ___cpu_t_current_OFFSET
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l32i a0, a0, _thread_offset_to_psp
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addi a0, a0, -___xtensa_irq_bsa_t_SIZEOF
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mov a1, a0
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l32i a3, a1, ___xtensa_irq_bsa_t_pc_OFFSET
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#if XCHAL_HAVE_LOOPS
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/* If the syscall instruction was the last instruction in the body of
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* a zero-overhead loop, and the loop will execute again, decrement
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* the loop count and resume execution at the head of the loop.
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*/
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rsr.lend a2
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addi a3, a3, 3
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bne a2, a3, end_loop
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rsr.lcount a2
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beqz a2, end_loop
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addi a2, a2, -1
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wsr.lcount a2
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rsr.lbeg a3
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end_loop:
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#else
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/* EPC1 (and now a3) contains the address that invoked syscall.
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* We need to increment it to execute the next instruction when
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* we return. The instruction size is 3 bytes, so lets just add it.
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*/
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addi a3, a3, 3
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#endif
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s32i a3, a1, ___xtensa_irq_bsa_t_pc_OFFSET
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ODD_REG_SAVE
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#if defined(CONFIG_XTENSA_HIFI_SHARING)
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call0 _xtensa_hifi_save
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#endif
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call0 xtensa_save_high_regs
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l32i a2, a1, 0
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l32i a2, a2, ___xtensa_irq_bsa_t_a2_OFFSET
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movi a0, K_SYSCALL_LIMIT
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bgeu a2, a0, _bad_syscall
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_id_ok:
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/* Find the function handler for the given syscall id. */
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movi a3, _k_syscall_table
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slli a2, a2, 2
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add a2, a2, a3
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l32i a2, a2, 0
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#if XCHAL_HAVE_THREADPTR
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/* Clear up the threadptr because it is used
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* to check if a thread is running on user mode. Since
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* we are in a interruption we don't want the system
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* thinking it is possibly running in user mode.
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*/
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#ifdef CONFIG_THREAD_LOCAL_STORAGE
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movi a0, is_user_mode@tpoff
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rur.THREADPTR a3
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add a0, a3, a0
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movi a3, 0
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s32i a3, a0, 0
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#else
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movi a0, 0
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wur.THREADPTR a0
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#endif
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#endif /* XCHAL_HAVE_THREADPTR */
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/* Set syscall parameters by moving them into place before we do
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* a call4 for the syscall function itself.
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* arg1 = a6
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* arg2 = a3 (clobbered above, so we need to reload it)
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* arg3 = a4
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* arg4 = a5
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* arg5 = a8
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* arg6 = a9
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*/
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mov a10, a8
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mov a11, a9
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mov a8, a4
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mov a9, a5
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/* Stack frame pointer is the 7th argument to z_mrsh_*()
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* as ssf, and must be put on stack to be consumed.
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*/
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mov a3, a1
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addi a1, a1, -4
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s32i a3, a1, 0
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l32i a3, a1, 4
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l32i a7, a3, ___xtensa_irq_bsa_t_a3_OFFSET
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/* Since we are unmasking EXCM, we need to set RING bits to kernel
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* mode, otherwise we won't be able to run the exception handler in C.
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*/
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movi a0, PS_WOE|PS_CALLINC(0)|PS_UM|PS_INTLEVEL(0)
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wsr.ps a0
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rsync
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callx4 a2
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/* Going back before stack frame pointer on stack to
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* actual the stack frame. So restoration of registers
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* can be done properly when finishing syscalls.
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*/
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addi a1, a1, 4
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/* copy return value. Lets put it in the top of stack
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* because registers will be clobbered in
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* xtensa_restore_high_regs
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*/
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l32i a3, a1, 0
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s32i a6, a3, ___xtensa_irq_bsa_t_a2_OFFSET
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j _syscall_returned
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_syscall_returned:
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call0 xtensa_restore_high_regs
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l32i a3, a1, ___xtensa_irq_bsa_t_sar_OFFSET
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wsr a3, SAR
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#if XCHAL_HAVE_LOOPS
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l32i a3, a1, ___xtensa_irq_bsa_t_lbeg_OFFSET
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wsr a3, LBEG
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l32i a3, a1, ___xtensa_irq_bsa_t_lend_OFFSET
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wsr a3, LEND
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l32i a3, a1, ___xtensa_irq_bsa_t_lcount_OFFSET
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wsr a3, LCOUNT
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#endif
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#if XCHAL_HAVE_S32C1I
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l32i a3, a1, ___xtensa_irq_bsa_t_scompare1_OFFSET
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wsr a3, SCOMPARE1
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#endif
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#if XCHAL_HAVE_THREADPTR
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#ifdef CONFIG_THREAD_LOCAL_STORAGE
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l32i a3, a1, ___xtensa_irq_bsa_t_threadptr_OFFSET
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movi a0, is_user_mode@tpoff
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add a0, a3, a0
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movi a3, 1
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s32i a3, a0, 0
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#else
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rsr a3, ZSR_CPU
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l32i a3, a3, ___cpu_t_current_OFFSET
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wur.THREADPTR a3
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#endif
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#endif /* XCHAL_HAVE_THREADPTR */
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l32i a3, a1, ___xtensa_irq_bsa_t_ps_OFFSET
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wsr.ps a3
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l32i a3, a1, ___xtensa_irq_bsa_t_pc_OFFSET
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wsr.epc1 a3
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l32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET
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l32i a2, a1, ___xtensa_irq_bsa_t_a2_OFFSET
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l32i a3, a1, ___xtensa_irq_bsa_t_a3_OFFSET
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l32i a1, a1, ___xtensa_irq_bsa_t_scratch_OFFSET
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rsync
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rfe
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_bad_syscall:
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movi a2, K_SYSCALL_BAD
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j _id_ok
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.popsection
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/* FUNC_NORETURN void xtensa_userspace_enter(k_thread_entry_t user_entry,
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* void *p1, void *p2, void *p3,
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* uint32_t stack_end,
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* uint32_t stack_start)
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*
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* A one-way trip to userspace.
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*/
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.global xtensa_userspace_enter
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.type xtensa_userspace_enter, @function
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.align 4
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xtensa_userspace_enter:
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/* Call entry to set a bit in the windowstart and
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* do the rotation, but we are going to set our own
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* stack.
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*/
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entry a1, 16
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/* We have to switch to kernel stack before spill kernel data and
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* erase user stack to avoid leak from previous context.
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*/
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mov a1, a7 /* stack start (low address) */
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addi a1, a1, -16
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SPILL_ALL_WINDOWS
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rsr a0, ZSR_CPU
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l32i a0, a0, ___cpu_t_current_OFFSET
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addi a1, a1, -28
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s32i a0, a1, 24
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s32i a2, a1, 20
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s32i a3, a1, 16
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s32i a4, a1, 12
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s32i a5, a1, 8
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s32i a6, a1, 4
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s32i a7, a1, 0
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l32i a6, a1, 24
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call4 xtensa_user_stack_perms
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l32i a6, a1, 24
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#ifdef CONFIG_XTENSA_MMU
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call4 xtensa_swap_update_page_tables
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#endif
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#ifdef CONFIG_XTENSA_MPU
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call4 xtensa_mpu_map_write
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#endif
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#if XCHAL_HAVE_THREADPTR
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#ifdef CONFIG_THREAD_LOCAL_STORAGE
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rur.threadptr a3
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movi a0, is_user_mode@tpoff
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add a0, a3, a0
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movi a3, 1
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s32i a3, a0, 0
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#else
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rsr a3, ZSR_CPU
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l32i a3, a3, ___cpu_t_current_OFFSET
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wur.THREADPTR a3
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#endif
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#endif /* XCHAL_HAVE_THREADPTR */
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/* Set now z_thread_entry parameters, we are simulating a call4
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* call, so parameters start at a6, a7, ...
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*/
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l32i a6, a1, 20
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l32i a7, a1, 16
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l32i a8, a1, 12
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l32i a9, a1, 8
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/* stash user stack */
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l32i a0, a1, 4
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/* Go back to user stack */
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mov a1, a0
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movi a0, z_thread_entry
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wsr.epc2 a0
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/* Configuring PS register.
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* We have to set callinc as well, since the called
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* function will do "entry"
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*/
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#ifdef CONFIG_XTENSA_MMU
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movi a0, PS_WOE|PS_CALLINC(1)|PS_UM|PS_RING(2)
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#endif
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#ifdef CONFIG_XTENSA_MPU
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/* MPU only has RING 0 and 1. */
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movi a0, PS_WOE|PS_CALLINC(1)|PS_UM|PS_RING(1)
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#endif
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wsr a0, EPS2
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movi a0, 0
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rfi 2
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/*
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* size_t arch_user_string_nlen(const char *s, size_t maxsize, int *err_arg)
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*/
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.global arch_user_string_nlen
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.type arch_user_string_nlen, @function
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.align 4
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arch_user_string_nlen:
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entry a1, 32
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/* error value, set to -1. */
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movi a5, -1
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s32i a5, a4, 0
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/* length count */
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xor a5, a5, a5
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/* This code might page fault */
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strlen_loop:
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.global xtensa_user_string_nlen_fault_start
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xtensa_user_string_nlen_fault_start:
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l8ui a6, a2, 0 /* Current char */
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.global xtensa_user_string_nlen_fault_end
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xtensa_user_string_nlen_fault_end:
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beqz a6, strlen_done
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addi a5, a5, 1
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addi a2, a2, 1
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beq a5, a3, strlen_done
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j strlen_loop
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strlen_done:
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/* Set return value */
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mov a2, a5
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/* Set error value to 0 since we succeeded */
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movi a5, 0x0
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s32i a5, a4, 0
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.global xtensa_user_string_nlen_fixup
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xtensa_user_string_nlen_fixup:
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retw
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