127 lines
2.2 KiB
Plaintext
127 lines
2.2 KiB
Plaintext
/*
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* Copyright (c) 2022 Nordic Semiconductor
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* SPDX-License-Identifier: Apache-2.0
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*/
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&pinctrl {
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uart0_default: uart0_default {
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group1 {
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psels = <NRF_PSEL(UART_TX, 1, 3)>,
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<NRF_PSEL(UART_RX, 1, 10)>;
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};
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};
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uart0_sleep: uart0_sleep {
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group1 {
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psels = <NRF_PSEL(UART_TX, 1, 3)>,
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<NRF_PSEL(UART_RX, 1, 10)>;
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low-power-enable;
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};
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};
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i2c0_default: i2c0_default {
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group1 {
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psels = <NRF_PSEL(TWIM_SDA, 0, 31)>,
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<NRF_PSEL(TWIM_SCL, 0, 2)>;
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};
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};
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i2c0_sleep: i2c0_sleep {
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group1 {
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psels = <NRF_PSEL(TWIM_SDA, 0, 31)>,
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<NRF_PSEL(TWIM_SCL, 0, 2)>;
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low-power-enable;
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};
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};
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i2c1_default: i2c1_default {
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group1 {
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psels = <NRF_PSEL(TWIM_SDA, 0, 14)>,
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<NRF_PSEL(TWIM_SCL, 0, 15)>;
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};
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};
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i2c1_sleep: i2c1_sleep {
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group1 {
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psels = <NRF_PSEL(TWIM_SDA, 0, 14)>,
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<NRF_PSEL(TWIM_SCL, 0, 15)>;
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low-power-enable;
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};
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};
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spi2_default: spi2_default {
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group1 {
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psels = <NRF_PSEL(SPIM_SCK, 0, 13)>,
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<NRF_PSEL(SPIM_MOSI, 1, 1)>,
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<NRF_PSEL(SPIM_MISO, 1, 8)>;
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};
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};
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spi2_sleep: spi2_sleep {
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group1 {
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psels = <NRF_PSEL(SPIM_SCK, 0, 13)>,
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<NRF_PSEL(SPIM_MOSI, 1, 1)>,
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<NRF_PSEL(SPIM_MISO, 1, 8)>;
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low-power-enable;
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};
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};
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pwm0_default: pwm0_default {
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group1 {
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psels = <NRF_PSEL(PWM_OUT0, 0, 24)>,
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<NRF_PSEL(PWM_OUT1, 0, 16)>,
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<NRF_PSEL(PWM_OUT2, 0, 6)>;
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nordic,invert;
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};
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};
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pwm0_sleep: pwm0_sleep {
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group1 {
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psels = <NRF_PSEL(PWM_OUT0, 0, 24)>,
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<NRF_PSEL(PWM_OUT1, 0, 16)>,
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<NRF_PSEL(PWM_OUT2, 0, 6)>;
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low-power-enable;
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};
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};
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pwm1_default: pwm1_default {
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group1 {
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psels = <NRF_PSEL(PWM_OUT0, 1, 9)>;
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};
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};
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pwm1_sleep: pwm1_sleep {
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group1 {
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psels = <NRF_PSEL(PWM_OUT0, 1, 9)>;
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};
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};
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pdm0_default: pdm0_default {
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group1 {
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psels = <NRF_PSEL(PDM_CLK, 0, 26)>,
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<NRF_PSEL(PDM_DIN, 0, 25)>;
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};
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};
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pdm0_sleep: pdm0_sleep {
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group1 {
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psels = <NRF_PSEL(PDM_CLK, 0, 26)>,
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<NRF_PSEL(PDM_DIN, 0, 25)>;
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low-power-enable;
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};
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};
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pwm2_default: pwm2_default {
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group1 {
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psels = <NRF_PSEL(PWM_OUT0, 0, 13)>;
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};
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};
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pwm2_sleep: pwm2_sleep {
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group1 {
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psels = <NRF_PSEL(PWM_OUT0, 0, 13)>;
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low-power-enable;
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};
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};
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};
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