246 lines
6.4 KiB
C
246 lines
6.4 KiB
C
/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief ARM Cortex-M interrupt management
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*
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*
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* Interrupt management: enabling/disabling and dynamic ISR
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* connecting/replacing. SW_ISR_TABLE_DYNAMIC has to be enabled for
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* connecting ISRs at runtime.
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <arch/arm/cortex_m/cmsis.h>
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#include <misc/__assert.h>
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#include <toolchain.h>
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#include <linker/sections.h>
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#include <sw_isr_table.h>
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#include <irq.h>
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#include <kernel_structs.h>
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#include <logging/kernel_event_logger.h>
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extern void __reserved(void);
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#define NUM_IRQS_PER_REG 32
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#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
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#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)
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/**
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*
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* @brief Enable an interrupt line
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*
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* Enable the interrupt. After this call, the CPU will receive interrupts for
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* the specified <irq>.
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*
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* @return N/A
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*/
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void _arch_irq_enable(unsigned int irq)
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{
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NVIC_EnableIRQ((IRQn_Type)irq);
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}
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/**
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*
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* @brief Disable an interrupt line
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*
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* Disable an interrupt line. After this call, the CPU will stop receiving
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* interrupts for the specified <irq>.
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*
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* @return N/A
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*/
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void _arch_irq_disable(unsigned int irq)
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{
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NVIC_DisableIRQ((IRQn_Type)irq);
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}
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/**
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* @brief Return IRQ enable state
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*
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* @param irq IRQ line
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* @return interrupt enable state, true or false
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*/
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int _arch_irq_is_enabled(unsigned int irq)
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{
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return NVIC->ISER[REG_FROM_IRQ(irq)] & (1 << BIT_FROM_IRQ(irq));
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}
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/**
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* @internal
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*
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* @brief Set an interrupt's priority
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*
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* The priority is verified if ASSERT_ON is enabled. The maximum number
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* of priority levels is a little complex, as there are some hardware
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* priority levels which are reserved.
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*
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* @return N/A
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*/
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void _irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags)
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{
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/* The kernel may reserve some of the highest priority levels.
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* So we offset the requested priority level with the number
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* of priority levels reserved by the kernel.
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*/
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#if CONFIG_ZERO_LATENCY_IRQS
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/* If we have zero latency interrupts, those interrupts will
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* run at a priority level which is not masked by irq_lock().
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* Our policy is to express priority levels with special properties
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* via flags
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*/
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if (flags & IRQ_ZERO_LATENCY) {
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prio = _EXC_ZERO_LATENCY_IRQS_PRIO;
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} else {
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prio += _IRQ_PRIO_OFFSET;
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}
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#else
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ARG_UNUSED(flags);
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prio += _IRQ_PRIO_OFFSET;
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#endif
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/* The last priority level is also used by PendSV exception, but
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* allow other interrupts to use the same level, even if it ends up
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* affecting performance (can still be useful on systems with a
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* reduced set of priorities, like Cortex-M0/M0+).
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*/
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__ASSERT(prio <= ((1 << CONFIG_NUM_IRQ_PRIO_BITS) - 1),
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"invalid priority %d! values must be less than %d\n",
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prio - _IRQ_PRIO_OFFSET,
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(1 << CONFIG_NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
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NVIC_SetPriority((IRQn_Type)irq, prio);
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}
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/**
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*
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* @brief Spurious interrupt handler
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*
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* Installed in all dynamic interrupt slots at boot time. Throws an error if
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* called.
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*
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* See __reserved().
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*
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* @return N/A
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*/
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void _irq_spurious(void *unused)
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{
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ARG_UNUSED(unused);
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__reserved();
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}
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/* FIXME: IRQ direct inline functions have to be placed here and not in
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* arch/cpu.h as inline functions due to nasty circular dependency between
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* arch/cpu.h and kernel_structs.h; the inline functions typically need to
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* perform operations on _kernel. For now, leave as regular functions, a
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* future iteration will resolve this.
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* We have a similar issue with the k_event_logger functions.
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*
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* See https://github.com/zephyrproject-rtos/zephyr/issues/3056
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*/
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#ifdef CONFIG_SYS_POWER_MANAGEMENT
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void _arch_isr_direct_pm(void)
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{
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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int key;
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/* irq_lock() does what we wan for this CPU */
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key = irq_lock();
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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/* Lock all interrupts. irq_lock() will on this CPU only disable those
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* lower than BASEPRI, which is not what we want. See comments in
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* arch/arm/core/isr_wrapper.S
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*/
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__asm__ volatile("cpsid i" : : : "memory");
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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if (_kernel.idle) {
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s32_t idle_val = _kernel.idle;
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_kernel.idle = 0;
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_sys_power_save_idle_exit(idle_val);
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}
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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irq_unlock(key);
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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__asm__ volatile("cpsie i" : : : "memory");
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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}
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#endif
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#if defined(CONFIG_KERNEL_EVENT_LOGGER_SLEEP) || \
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defined(CONFIG_KERNEL_EVENT_LOGGER_INTERRUPT)
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void _arch_isr_direct_header(void)
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{
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_sys_k_event_logger_interrupt();
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_sys_k_event_logger_exit_sleep();
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}
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#endif
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#if defined(CONFIG_ARM_SECURE_FIRMWARE)
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/**
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*
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* @brief Set the target security state for the given IRQ
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*
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* Function sets the security state (Secure or Non-Secure) targeted
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* by the given irq. It requires ARMv8-M MCU.
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* It is only compiled if ARM_SECURE_FIRMWARE is defined.
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* It should only be called while in Secure state, otherwise, a write attempt
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* to NVIC.ITNS register is write-ignored(WI), as the ITNS register is not
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* banked between security states and, therefore, has no Non-Secure instance.
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*
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* It shall assert if the operation is not performed successfully.
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*
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* @param irq IRQ line
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* @param secure_state 1 if target state is Secure, 0 otherwise.
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*
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* @return N/A
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*/
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void irq_target_state_set(unsigned int irq, int secure_state)
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{
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if (secure_state) {
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/* Set target to Secure */
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if (NVIC_ClearTargetState(irq) != 0) {
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__ASSERT(0, "NVIC SetTargetState error");
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}
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} else {
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/* Set target state to Non-Secure */
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if (NVIC_SetTargetState(irq) != 1) {
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__ASSERT(0, "NVIC SetTargetState error");
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}
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}
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}
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/**
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*
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* @brief Determine whether the given IRQ targets the Secure state
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*
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* Function determines whether the given irq targets the Secure state
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* or not (i.e. targets the Non-Secure state). It requires ARMv8-M MCU.
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* It is only compiled if ARM_SECURE_FIRMWARE is defined.
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* It should only be called while in Secure state, otherwise, a read attempt
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* to NVIC.ITNS register is read-as-zero(RAZ), as the ITNS register is not
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* banked between security states and, therefore, has no Non-Secure instance.
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*
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* @param irq IRQ line
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*
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* @return 1 if target state is Secure, 0 otherwise.
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*/
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int irq_target_state_is_secure(unsigned int irq)
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{
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return NVIC_GetTargetState(irq) == 0;
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}
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#endif /* CONFIG_ARM_SECURE_FIRMWARE */
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