65 lines
2.0 KiB
YAML
65 lines
2.0 KiB
YAML
# Copyright 2022 NXP
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# SPDX-License-Identifier: Apache-2.0
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description: |
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NXP S32 Message Receive Unit
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The MRU couples with a processor and allows to receive messages from senders,
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which are other modules or processors. The interrupts from each MRU instance
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route to specific Private Peripheral Interrupts (PPIs) of the corresponding
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core.
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This driver offers a simplified operation in order to integrate with Zephyr
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Mbox API:
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- Each channel uses only the first mailbox, as current API does not allow
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to group hardware channel's mailboxes in logical channels.
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- The MTU is fixed to the size of one mailbox, as current API does not
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allow variable length per channel.
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In a normal use-case for IPC, the receiver core must enable and set the number
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of receive channels on the MRU instance coupled with the core, for instance in
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a devicetree overlay. In turn, the sender(s) must enable the MRU instance of the
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receiver to be able to transmit on it. There is no need to define the transmit
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channels on which the sender is intended to transmit.
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For example, core B and C want to send messages to core A in channels 0 and 1,
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respectively, then the devicetree overlays will look like:
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// overlay of core A
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mruA {
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rx-channels = <2>;
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status = "okay";
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};
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// overlays of core B and core C
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mruA {
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status = "okay";
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};
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compatible: "nxp,s32-mru"
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include: [base.yaml, mailbox-controller.yaml]
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properties:
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interrupts:
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required: true
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rx-channels:
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type: int
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enum: [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12]
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description: |
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Number of receive channels enabled on this instance.
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Setting this value to N, will enable channels 0 to N-1, consecutively.
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It should be set by the receiver core coupled with this MRU instance.
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For example, if receiver A wants to Rx on channels 0 and 1, then A must
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set rx-channels of mruA as follows:
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mruA {
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rx-channels = <2>;
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status = "okay";
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};
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mbox-cells:
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- channel
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