86 lines
1.9 KiB
C
86 lines
1.9 KiB
C
/*
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* Copyright (c) 2022 Basalte bv
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* Copyright (c) 2023 Gerson Fernando Budke
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT atmel_sam_rstc
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#include <zephyr/device.h>
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#include <zephyr/drivers/hwinfo.h>
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#include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
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BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
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"No atmel,sam-rstc compatible device found");
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int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
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{
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/* Get reason from Status Register */
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uint32_t reason = ((Rstc *)DT_INST_REG_ADDR(0))->RSTC_SR & RSTC_SR_RSTTYP_Msk;
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switch (reason) {
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case RSTC_SR_RSTTYP_GENERAL_RST:
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*cause = RESET_POR;
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break;
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case RSTC_SR_RSTTYP_BACKUP_RST:
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*cause = RESET_LOW_POWER_WAKE;
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break;
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case RSTC_SR_RSTTYP_WDT_RST:
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*cause = RESET_WATCHDOG;
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break;
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case RSTC_SR_RSTTYP_SOFT_RST:
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*cause = RESET_SOFTWARE;
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break;
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case RSTC_SR_RSTTYP_USER_RST:
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*cause = RESET_USER;
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break;
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default:
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break;
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}
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return 0;
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}
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int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
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{
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*supported = RESET_POR
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| RESET_LOW_POWER_WAKE
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| RESET_WATCHDOG
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| RESET_SOFTWARE
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| RESET_USER;
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return 0;
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}
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static int hwinfo_rstc_init(void)
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{
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Rstc *regs = (Rstc *)DT_INST_REG_ADDR(0);
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const struct atmel_sam_pmc_config clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(0);
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uint32_t mode;
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/* Enable RSTC in PMC */
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(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
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(clock_control_subsys_t)&clock_cfg);
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/* Get current Mode Register value */
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mode = regs->RSTC_MR;
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/* Enable/disable user reset on NRST */
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#if DT_INST_PROP(0, user_nrst)
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mode &= ~RSTC_MR_KEY_Msk;
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mode |= (RSTC_MR_URSTEN | RSTC_MR_KEY_PASSWD);
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#else
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mode &= ~(RSTC_MR_URSTEN | RSTC_MR_KEY_Msk);
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mode |= RSTC_MR_KEY_PASSWD;
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#endif
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/* Set Mode Register value */
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regs->RSTC_MR = mode;
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return 0;
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}
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SYS_INIT(hwinfo_rstc_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
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