102 lines
2.8 KiB
C
102 lines
2.8 KiB
C
/*
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* Copyright (c) 2022 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_imx_src_rev2
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#include <soc.h>
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#include <zephyr/drivers/hwinfo.h>
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#include <string.h>
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#include <zephyr/sys/byteorder.h>
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#include <fsl_soc_src.h>
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#ifdef CONFIG_CPU_CORTEX_M7
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#define MCUX_RESET_PIN_FLAG kSRC_M7CoreIppUserResetFlag
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#define MCUX_RESET_SOFTWARE_FLAG kSRC_M7CoreM7LockUpResetFlag
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#define MCUX_RESET_POR_FLAG kSRC_M7CoreIppResetFlag
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#define MCUX_RESET_WATCHDOG_FLAG (kSRC_M7CoreWdogResetFlag | \
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kSRC_M7CoreWdog3ResetFlag | \
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kSRC_M7CoreWdog4ResetFlag)
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#define MCUX_RESET_DEBUG_FLAG kSRC_M7CoreJtagResetFlag
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#define MCUX_RESET_SECURITY_FLAG kSRC_M7CoreCSUResetFlag
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#define MCUX_RESET_TEMPERATURE_FLAG kSRC_M7CoreTempsenseResetFlag
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#define MCUX_RESET_USER_FLAG kSRC_M7CoreM7RequestResetFlag
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#elif defined(CONFIG_CPU_CORTEX_M4)
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#define MCUX_RESET_PIN_FLAG kSRC_M4CoreIppUserResetFlag
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#define MCUX_RESET_SOFTWARE_FLAG kSRC_M4CoreM7LockUpResetFlag
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#define MCUX_RESET_POR_FLAG kSRC_M4CoreIppResetFlag
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#define MCUX_RESET_WATCHDOG_FLAG (kSRC_M4CoreWdogResetFlag | \
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kSRC_M4CoreWdog3ResetFlag | \
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kSRC_M4CoreWdog4ResetFlag)
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#define MCUX_RESET_DEBUG_FLAG kSRC_M4CoreJtagResetFlag
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#define MCUX_RESET_SECURITY_FLAG kSRC_M4CoreCSUResetFlag
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#define MCUX_RESET_TEMPERATURE_FLAG kSRC_M4CoreTempsenseResetFlag
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#define MCUX_RESET_USER_FLAG kSRC_M4CoreM7RequestResetFlag
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#else
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/* The SOCs currently supported have an M7 or M4 core */
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#error "MCUX SRC driver not supported for this CPU!"
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#endif
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BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, "No nxp,imx-src compatible device found");
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int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
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{
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uint32_t flags = 0;
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uint32_t reason = SRC_GetResetStatusFlags((SRC_Type *)DT_INST_REG_ADDR(0));
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if (reason & (MCUX_RESET_PIN_FLAG)) {
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flags |= RESET_PIN;
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}
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if (reason & (MCUX_RESET_SOFTWARE_FLAG)) {
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flags |= RESET_SOFTWARE;
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}
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if (reason & (MCUX_RESET_POR_FLAG)) {
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flags |= RESET_POR;
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}
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if (reason & (MCUX_RESET_WATCHDOG_FLAG)) {
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flags |= RESET_WATCHDOG;
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}
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if (reason & (MCUX_RESET_DEBUG_FLAG)) {
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flags |= RESET_DEBUG;
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}
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if (reason & (MCUX_RESET_SECURITY_FLAG)) {
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flags |= RESET_SECURITY;
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}
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if (reason & (MCUX_RESET_TEMPERATURE_FLAG)) {
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flags |= RESET_TEMPERATURE;
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}
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if (reason & (MCUX_RESET_USER_FLAG)) {
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flags |= RESET_USER;
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}
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*cause = flags;
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return 0;
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}
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int z_impl_hwinfo_clear_reset_cause(void)
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{
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uint32_t reason = SRC_GetResetStatusFlags((SRC_Type *)DT_INST_REG_ADDR(0));
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SRC_ClearGlobalSystemResetStatus((SRC_Type *)DT_INST_REG_ADDR(0), reason);
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return 0;
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}
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int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
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{
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*supported = (RESET_WATCHDOG
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| RESET_DEBUG
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| RESET_TEMPERATURE
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| RESET_PIN
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| RESET_SOFTWARE
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| RESET_POR
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| RESET_SECURITY
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| RESET_USER
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);
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return 0;
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}
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