159 lines
4.6 KiB
C
159 lines
4.6 KiB
C
/*
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* Copyright (c) 2019 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_AUDIO_TLV320DAC310X_H_
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#define ZEPHYR_DRIVERS_AUDIO_TLV320DAC310X_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Register addresses */
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#define PAGE_CONTROL_ADDR 0
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/* Register addresses {page, address} and fields */
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#define SOFT_RESET_ADDR (struct reg_addr){0, 1}
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#define SOFT_RESET_ASSERT (1)
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#define NDAC_DIV_ADDR (struct reg_addr){0, 11}
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#define NDAC_POWER_UP BIT(7)
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#define NDAC_POWER_UP_MASK BIT(7)
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#define NDAC_DIV_MASK BIT_MASK(7)
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#define NDAC_DIV(val) ((val) & NDAC_DIV_MASK)
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#define MDAC_DIV_ADDR (struct reg_addr){0, 12}
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#define MDAC_POWER_UP BIT(7)
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#define MDAC_POWER_UP_MASK BIT(7)
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#define MDAC_DIV_MASK BIT_MASK(7)
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#define MDAC_DIV(val) ((val) & MDAC_DIV_MASK)
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#define DAC_PROC_CLK_FREQ_MAX 49152000 /* 49.152 MHz */
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#define OSR_MSB_ADDR (struct reg_addr){0, 13}
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#define OSR_MSB_MASK BIT_MASK(2)
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#define OSR_LSB_ADDR (struct reg_addr){0, 14}
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#define OSR_LSB_MASK BIT_MASK(8)
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#define DAC_MOD_CLK_FREQ_MIN 2800000 /* 2.8 MHz */
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#define DAC_MOD_CLK_FREQ_MAX 6200000 /* 6.2 MHz */
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#define IF_CTRL1_ADDR (struct reg_addr){0, 27}
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#define IF_CTRL_IFTYPE_MASK BIT_MASK(2)
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#define IF_CTRL_IFTYPE_I2S 0
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#define IF_CTRL_IFTYPE_DSP 1
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#define IF_CTRL_IFTYPE_RJF 2
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#define IF_CTRL_IFTYPE_LJF 3
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#define IF_CTRL_IFTYPE(val) (((val) & IF_CTRL_IFTYPE_MASK) << 6)
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#define IF_CTRL_WLEN_MASK BIT_MASK(2)
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#define IF_CTRL_WLEN(val) (((val) & IF_CTRL_WLEN_MASK) << 4)
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#define IF_CTRL_WLEN_16 0
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#define IF_CTRL_WLEN_20 1
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#define IF_CTRL_WLEN_24 2
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#define IF_CTRL_WLEN_32 3
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#define IF_CTRL_BCLK_OUT BIT(3)
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#define IF_CTRL_WCLK_OUT BIT(2)
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#define BCLK_DIV_ADDR (struct reg_addr){0, 30}
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#define BCLK_DIV_POWER_UP BIT(7)
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#define BCLK_DIV_POWER_UP_MASK BIT(7)
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#define BCLK_DIV_MASK BIT_MASK(7)
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#define BCLK_DIV(val) ((val) & MDAC_DIV_MASK)
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#define OVF_FLAG_ADDR (struct reg_addr){0, 39}
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#define PROC_BLK_SEL_ADDR (struct reg_addr){0, 60}
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#define PROC_BLK_SEL_MASK BIT_MASK(5)
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#define PROC_BLK_SEL(val) ((val) & PROC_BLK_SEL_MASK)
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#define DATA_PATH_SETUP_ADDR (struct reg_addr){0, 63}
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#define DAC_LR_POWERUP_DEFAULT (BIT(7) | BIT(6) | BIT(4) | BIT(2))
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#define DAC_LR_POWERDN_DEFAULT (BIT(4) | BIT(2))
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#define VOL_CTRL_ADDR (struct reg_addr){0, 64}
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#define VOL_CTRL_UNMUTE_DEFAULT (0)
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#define VOL_CTRL_MUTE_DEFAULT (BIT(3) | BIT(2))
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#define L_DIG_VOL_CTRL_ADDR (struct reg_addr){0, 65}
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#define DRC_CTRL1_ADDR (struct reg_addr){0, 68}
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#define L_BEEP_GEN_ADDR (struct reg_addr){0, 71}
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#define BEEP_GEN_EN_BEEP (BIT(7))
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#define R_BEEP_GEN_ADDR (struct reg_addr){0, 72}
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#define BEEP_LEN_MSB_ADDR (struct reg_addr){0, 73}
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#define BEEP_LEN_MIB_ADDR (struct reg_addr){0, 74}
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#define BEEP_LEN_LSB_ADDR (struct reg_addr){0, 75}
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/* Page 1 registers */
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#define HEADPHONE_DRV_ADDR (struct reg_addr){1, 31}
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#define HEADPHONE_DRV_POWERUP (BIT(7) | BIT(6))
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#define HEADPHONE_DRV_CM_MASK (BIT_MASK(2) << 3)
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#define HEADPHONE_DRV_CM(val) (((val) << 3) & HEADPHONE_DRV_CM_MASK)
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#define HEADPHONE_DRV_RESERVED (BIT(2))
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#define HP_OUT_POP_RM_ADDR (struct reg_addr){1, 33}
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#define HP_OUT_POP_RM_ENABLE (BIT(7))
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#define OUTPUT_ROUTING_ADDR (struct reg_addr){1, 35}
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#define OUTPUT_ROUTING_HPL (2 << 6)
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#define OUTPUT_ROUTING_HPR (2 << 2)
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#define HPL_ANA_VOL_CTRL_ADDR (struct reg_addr){1, 36}
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#define HPR_ANA_VOL_CTRL_ADDR (struct reg_addr){1, 37}
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#define HPX_ANA_VOL_ENABLE (BIT(7))
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#define HPX_ANA_VOL_MASK (BIT_MASK(7))
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#define HPX_ANA_VOL(val) (((val) & HPX_ANA_VOL_MASK) | \
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HPX_ANA_VOL_ENABLE)
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#define HPX_ANA_VOL_MAX (0)
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#define HPX_ANA_VOL_DEFAULT (64)
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#define HPX_ANA_VOL_MIN (127)
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#define HPX_ANA_VOL_MUTE (HPX_ANA_VOL_MIN | ~HPX_ANA_VOL_ENABLE)
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#define HPX_ANA_VOL_LOW_THRESH (105)
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#define HPX_ANA_VOL_FLOOR (144)
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#define HPL_DRV_GAIN_CTRL_ADDR (struct reg_addr){1, 40}
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#define HPR_DRV_GAIN_CTRL_ADDR (struct reg_addr){1, 41}
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#define HPX_DRV_UNMUTE (BIT(2))
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#define HEADPHONE_DRV_CTRL_ADDR (struct reg_addr){1, 44}
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#define HEADPHONE_DRV_LINEOUT (BIT(1) | BIT(2))
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/* Page 3 registers */
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#define TIMER_MCLK_DIV_ADDR (struct reg_addr){3, 16}
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#define TIMER_MCLK_DIV_EN_EXT (BIT(7))
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#define TIMER_MCLK_DIV_MASK (BIT_MASK(7))
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#define TIMER_MCLK_DIV_VAL(val) ((val) & TIMER_MCLK_DIV_MASK)
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struct reg_addr {
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uint8_t page; /* page number */
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uint8_t reg_addr; /* register address */
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};
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enum proc_block {
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/* highest performance class with each decimation filter */
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PRB_P25_DECIMATION_A = 25,
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PRB_P10_DECIMATION_B = 10,
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PRB_P18_DECIMATION_C = 18,
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};
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enum osr_multiple {
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OSR_MULTIPLE_8 = 8,
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OSR_MULTIPLE_4 = 4,
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OSR_MULTIPLE_2 = 2,
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};
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enum cm_voltage {
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CM_VOLTAGE_1P35 = 0,
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CM_VOLTAGE_1P5 = 1,
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CM_VOLTAGE_1P65 = 2,
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CM_VOLTAGE_1P8 = 3,
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_DRIVERS_AUDIO_TLV320DAC310X_H_ */
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