216 lines
4.8 KiB
ArmAsm
216 lines
4.8 KiB
ArmAsm
/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Reset handler
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*
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* Reset handler that prepares the system for running C code.
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*/
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#include <zephyr/toolchain.h>
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#include <zephyr/linker/sections.h>
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#include <zephyr/arch/cpu.h>
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#include <swap_macros.h>
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#include <zephyr/arch/arc/asm-compat/assembler.h>
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#ifdef CONFIG_ARC_EARLY_SOC_INIT
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#include <soc_ctrl.h>
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#endif
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GDATA(z_interrupt_stacks)
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GDATA(z_main_stack)
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GDATA(_VectorTable)
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/* use one of the available interrupt stacks during init */
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#define INIT_STACK z_interrupt_stacks
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#define INIT_STACK_SIZE CONFIG_ISR_STACK_SIZE
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GTEXT(__reset)
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GTEXT(__start)
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/**
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* @brief Reset vector
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*
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* Ran when the system comes out of reset. The processor is at supervisor level.
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*
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* Locking interrupts prevents anything from interrupting the CPU.
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*
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* When these steps are completed, jump to z_prep_c(), which will finish setting
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* up the system for running C code.
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*/
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SECTION_SUBSEC_FUNC(TEXT,_reset_and__start,__reset)
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SECTION_SUBSEC_FUNC(TEXT,_reset_and__start,__start)
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/* lock interrupts: will get unlocked when switch to main task
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* also make sure the processor in the correct status
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*/
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mov_s r0, 0
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kflag r0
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#ifdef CONFIG_ARC_SECURE_FIRMWARE
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sflag r0
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#endif
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/* interrupt related init */
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#ifndef CONFIG_ARC_NORMAL_FIRMWARE
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/* IRQ_ACT and IRQ_CTRL should be initialized and set in secure mode */
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sr r0, [_ARC_V2_AUX_IRQ_ACT]
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sr r0, [_ARC_V2_AUX_IRQ_CTRL]
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#endif
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sr r0, [_ARC_V2_AUX_IRQ_HINT]
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/* set the vector table base early,
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* so that exception vectors can be handled.
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*/
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MOVR r0, _VectorTable
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#ifdef CONFIG_ARC_SECURE_FIRMWARE
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sr r0, [_ARC_V2_IRQ_VECT_BASE_S]
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#else
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SRR r0, [_ARC_V2_IRQ_VECT_BASE]
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#endif
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lr r0, [_ARC_V2_STATUS32]
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bset r0, r0, _ARC_V2_STATUS32_DZ_BIT
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kflag r0
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#if defined(CONFIG_USERSPACE)
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lr r0, [_ARC_V2_STATUS32]
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bset r0, r0, _ARC_V2_STATUS32_US_BIT
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kflag r0
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#endif
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#ifdef CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS
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lr r0, [_ARC_V2_STATUS32]
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bset r0, r0, _ARC_V2_STATUS32_AD_BIT
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kflag r0
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#endif
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/* Invalidate icache */
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lr r0, [_ARC_V2_I_CACHE_BUILD]
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and.f r0, r0, 0xff
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bz.nd done_icache_invalidate
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mov_s r2, 0
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sr r2, [_ARC_V2_IC_IVIC]
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/* writing to IC_IVIC needs 3 NOPs */
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nop_s
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nop_s
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nop_s
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done_icache_invalidate:
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/* Invalidate dcache */
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lr r3, [_ARC_V2_D_CACHE_BUILD]
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and.f r3, r3, 0xff
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bz.nd done_dcache_invalidate
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mov_s r1, 1
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sr r1, [_ARC_V2_DC_IVDC]
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done_dcache_invalidate:
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#ifdef CONFIG_ARC_EARLY_SOC_INIT
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soc_early_asm_init_percpu
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#endif
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_dsp_extension_probe
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/*
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* Init ARC internal architecture state
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* Force to initialize internal architecture state to reset values
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* For scenarios where board hardware is not re-initialized between tests,
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* some settings need to be restored to its default initial states as a
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* substitution of normal hardware reset sequence.
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*/
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#ifdef CONFIG_INIT_ARCH_HW_AT_BOOT
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/* Set MPU (v4 or v8) registers to default */
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#if CONFIG_ARC_MPU_VER == 4 || CONFIG_ARC_MPU_VER == 8
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/* Set default reset value to _ARC_V2_MPU_EN register */
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#define ARC_MPU_EN_RESET_VALUE 0x400181C0
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mov_s r1, ARC_MPU_EN_RESET_VALUE
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sr r1, [_ARC_V2_MPU_EN]
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/* Get MPU region numbers */
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lr r3, [_ARC_V2_MPU_BUILD]
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lsr_s r3, r3, 8
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and r3, r3, 0xff
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mov_s r1, 0
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mov_s r2, 0
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/* Set all MPU regions by iterating index */
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mpu_regions_reset:
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brge r2, r3, done_mpu_regions_reset
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sr r2, [_ARC_V2_MPU_INDEX]
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sr r1, [_ARC_V2_MPU_RSTART]
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sr r1, [_ARC_V2_MPU_REND]
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sr r1, [_ARC_V2_MPU_RPER]
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add_s r2, r2, 1
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b_s mpu_regions_reset
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done_mpu_regions_reset:
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#endif
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#endif
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#ifdef CONFIG_ISA_ARCV3
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/* Enable HW prefetcher if exist */
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lr r0, [_ARC_HW_PF_BUILD]
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breq r0, 0, hw_pf_setup_done
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lr r1, [_ARC_HW_PF_CTRL]
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or r1, r1, _ARC_HW_PF_CTRL_ENABLE
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sr r1, [_ARC_HW_PF_CTRL]
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hw_pf_setup_done:
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#endif
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#if defined(CONFIG_SMP) || CONFIG_MP_MAX_NUM_CPUS > 1
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_get_cpu_id r0
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breq r0, 0, _master_core_startup
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/*
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* Non-masters wait for master core (core 0) to boot enough
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*/
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_slave_core_wait:
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#if CONFIG_MP_MAX_NUM_CPUS == 1
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kflag 1
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#endif
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ld r1, [arc_cpu_wake_flag]
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brne r0, r1, _slave_core_wait
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LDR sp, arc_cpu_sp
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/* signal master core that slave core runs */
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st 0, [arc_cpu_wake_flag]
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#if defined(CONFIG_ARC_FIRQ_STACK)
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push r0
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jl z_arc_firq_stack_set
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pop r0
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#endif
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j arch_secondary_cpu_init
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_master_core_startup:
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#endif
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#ifdef CONFIG_INIT_STACKS
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/*
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* use the main stack to call memset on the interrupt stack and the
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* FIRQ stack when CONFIG_INIT_STACKS is enabled before switching to
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* one of them for the rest of the early boot
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*/
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mov_s sp, z_main_stack
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add sp, sp, CONFIG_MAIN_STACK_SIZE
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mov_s r0, z_interrupt_stacks
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mov_s r1, 0xaa
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mov_s r2, CONFIG_ISR_STACK_SIZE
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jl memset
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#endif /* CONFIG_INIT_STACKS */
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mov_s sp, INIT_STACK
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add sp, sp, INIT_STACK_SIZE
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#if defined(CONFIG_ARC_FIRQ_STACK)
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jl z_arc_firq_stack_set
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#endif
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j z_prep_c
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