119 lines
5.5 KiB
C
119 lines
5.5 KiB
C
/*
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* Copyright (c) 2018 Savoir-Faire Linux.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __SPI_NOR_H__
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#define __SPI_NOR_H__
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#include <zephyr/sys/util.h>
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#define SPI_NOR_MAX_ID_LEN 3
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/* Status register bits */
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#define SPI_NOR_WIP_BIT BIT(0) /* Write in progress */
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#define SPI_NOR_WEL_BIT BIT(1) /* Write enable latch */
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/* Flash opcodes */
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#define SPI_NOR_CMD_WRSR 0x01 /* Write status register */
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#define SPI_NOR_CMD_RDSR 0x05 /* Read status register */
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#define SPI_NOR_CMD_WRSR2 0x31 /* Write status register 2 */
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#define SPI_NOR_CMD_RDSR2 0x35 /* Read status register 2 */
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#define SPI_NOR_CMD_RDSR3 0x15 /* Read status register 3 */
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#define SPI_NOR_CMD_WRSR3 0x11 /* Write status register 3 */
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#define SPI_NOR_CMD_READ 0x03 /* Read data */
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#define SPI_NOR_CMD_READ_FAST 0x0B /* Read data */
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#define SPI_NOR_CMD_DREAD 0x3B /* Read data (1-1-2) */
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#define SPI_NOR_CMD_2READ 0xBB /* Read data (1-2-2) */
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#define SPI_NOR_CMD_QREAD 0x6B /* Read data (1-1-4) */
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#define SPI_NOR_CMD_4READ 0xEB /* Read data (1-4-4) */
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#define SPI_NOR_CMD_WREN 0x06 /* Write enable */
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#define SPI_NOR_CMD_WRDI 0x04 /* Write disable */
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#define SPI_NOR_CMD_PP 0x02 /* Page program */
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#define SPI_NOR_CMD_PP_1_1_2 0xA2 /* Dual Page program (1-1-2) */
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#define SPI_NOR_CMD_PP_1_1_4 0x32 /* Quad Page program (1-1-4) */
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#define SPI_NOR_CMD_PP_1_4_4 0x38 /* Quad Page program (1-4-4) */
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#define SPI_NOR_CMD_RDCR 0x15 /* Read control register */
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#define SPI_NOR_CMD_SE 0x20 /* Sector erase */
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#define SPI_NOR_CMD_SE_4B 0x21 /* Sector erase 4 byte address*/
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#define SPI_NOR_CMD_BE_32K 0x52 /* Block erase 32KB */
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#define SPI_NOR_CMD_BE 0xD8 /* Block erase */
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#define SPI_NOR_CMD_CE 0xC7 /* Chip erase */
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#define SPI_NOR_CMD_RDID 0x9F /* Read JEDEC ID */
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#define SPI_NOR_CMD_ULBPR 0x98 /* Global Block Protection Unlock */
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#define SPI_NOR_CMD_4BA 0xB7 /* Enter 4-Byte Address Mode */
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#define SPI_NOR_CMD_DPD 0xB9 /* Deep Power Down */
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#define SPI_NOR_CMD_RDPD 0xAB /* Release from Deep Power Down */
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#define SPI_NOR_CMD_WR_CFGREG2 0x72 /* Write config register 2 */
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#define SPI_NOR_CMD_RD_CFGREG2 0x71 /* Read config register 2 */
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#define SPI_NOR_CMD_RESET_EN 0x66 /* Reset Enable */
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#define SPI_NOR_CMD_RESET_MEM 0x99 /* Reset Memory */
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#define SPI_NOR_CMD_BULKE 0x60 /* Bulk Erase */
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#define SPI_NOR_CMD_READ_4B 0x13 /* Read data 4 Byte Address */
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#define SPI_NOR_CMD_READ_FAST_4B 0x0C /* Fast Read 4 Byte Address */
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#define SPI_NOR_CMD_DREAD_4B 0x3C /* Read data (1-1-2) 4 Byte Address */
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#define SPI_NOR_CMD_2READ_4B 0xBC /* Read data (1-2-2) 4 Byte Address */
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#define SPI_NOR_CMD_QREAD_4B 0x6C /* Read data (1-1-4) 4 Byte Address */
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#define SPI_NOR_CMD_4READ_4B 0xEC /* Read data (1-4-4) 4 Byte Address */
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#define SPI_NOR_CMD_PP_4B 0x12 /* Page Program 4 Byte Address */
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#define SPI_NOR_CMD_PP_1_1_4_4B 0x34 /* Quad Page program (1-1-4) 4 Byte Address */
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#define SPI_NOR_CMD_PP_1_4_4_4B 0x3e /* Quad Page program (1-4-4) 4 Byte Address */
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/* Flash octal opcodes */
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#define SPI_NOR_OCMD_SE 0x21DE /* Octal Sector erase */
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#define SPI_NOR_OCMD_CE 0xC738 /* Octal Chip erase */
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#define SPI_NOR_OCMD_RDSR 0x05FA /* Octal Read status register */
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#define SPI_NOR_OCMD_DTR_RD 0xEE11 /* Octal IO DTR read command */
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#define SPI_NOR_OCMD_RD 0xEC13 /* Octal IO read command */
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#define SPI_NOR_OCMD_PAGE_PRG 0x12ED /* Octal Page Prog */
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#define SPI_NOR_OCMD_WREN 0x06F9 /* Octal Write enable */
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#define SPI_NOR_OCMD_NOP 0x00FF /* Octal No operation */
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#define SPI_NOR_OCMD_RESET_EN 0x6699 /* Octal Reset Enable */
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#define SPI_NOR_OCMD_RESET_MEM 0x9966 /* Octal Reset Memory */
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#define SPI_NOR_OCMD_WR_CFGREG2 0x728D /* Octal Write configuration Register2 */
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#define SPI_NOR_OCMD_RD_CFGREG2 0x718E /* Octal Read configuration Register2 */
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#define SPI_NOR_OCMD_BULKE 0x609F /* Octa Bulk Erase */
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/* Page, sector, and block size are standard, not configurable. */
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#define SPI_NOR_PAGE_SIZE 0x0100U
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#define SPI_NOR_SECTOR_SIZE 0x1000U
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#define SPI_NOR_BLOCK_SIZE 0x10000U
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/* Flash Auto-polling values */
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#define SPI_NOR_WREN_MATCH 0x02
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#define SPI_NOR_WREN_MASK 0x02
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#define SPI_NOR_WEL_MATCH 0x00
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#define SPI_NOR_WEL_MASK 0x02
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#define SPI_NOR_MEM_RDY_MATCH 0x00
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#define SPI_NOR_MEM_RDY_MASK 0x01
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#define SPI_NOR_AUTO_POLLING_INTERVAL 0x10
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/* Flash Dummy Cycles values */
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#define SPI_NOR_DUMMY_RD 8U
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#define SPI_NOR_DUMMY_RD_OCTAL 6U
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#define SPI_NOR_DUMMY_RD_OCTAL_DTR 6U
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#define SPI_NOR_DUMMY_REG_OCTAL 4U
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#define SPI_NOR_DUMMY_REG_OCTAL_DTR 5U
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/* Memory registers address */
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#define SPI_NOR_REG2_ADDR1 0x0000000
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#define SPI_NOR_CR2_STR_OPI_EN 0x01
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#define SPI_NOR_CR2_DTR_OPI_EN 0x02
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#define SPI_NOR_REG2_ADDR3 0x00000300
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#define SPI_NOR_CR2_DUMMY_CYCLES_66MHZ 0x07
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/* Test whether offset is aligned to a given number of bits. */
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#define SPI_NOR_IS_ALIGNED(_ofs, _bits) (((_ofs) & BIT_MASK(_bits)) == 0)
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#define SPI_NOR_IS_SECTOR_ALIGNED(_ofs) SPI_NOR_IS_ALIGNED(_ofs, 12)
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#define SPI_NOR_IS_32K_ALIGNED(_ofs) SPI_NOR_IS_ALIGNED(_ofs, 15)
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#define SPI_NOR_IS_64K_ALIGNED(_ofs) SPI_NOR_IS_ALIGNED(_ofs, 16)
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#define CMD_RDCR 0x15 /* Read the configuration register. */
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#endif /*__SPI_NOR_H__*/
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