378 lines
13 KiB
C
378 lines
13 KiB
C
/*
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* Copyright (c) 2023, Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef CDNS_NAND_LL_H
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#define CDNS_NAND_LL_H
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#include <zephyr/device.h>
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#include <zephyr/kernel.h>
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#include <zephyr/logging/log.h>
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#define NAND_INT_SEM_TAKE(param_ptr) \
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COND_CODE_1(IS_ENABLED(CONFIG_CDNS_NAND_INTERRUPT_SUPPORT), \
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(k_sem_take(&(param_ptr->interrupt_sem_t), K_FOREVER)), ())
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#define CNF_GET_INIT_COMP(x) (FIELD_GET(BIT(9), x))
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#define CNF_GET_INIT_FAIL(x) (FIELD_GET(BIT(10), x))
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#define CNF_GET_CTRL_BUSY(x) (FIELD_GET(BIT(8), x))
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#define GET_PAGE_SIZE(x) (FIELD_GET(GENMASK(15, 0), x))
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#define GET_PAGES_PER_BLOCK(x) (FIELD_GET(GENMASK(15, 0), x))
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#define GET_SPARE_SIZE(x) (FIELD_GET(GENMASK(31, 16), x))
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#define ONFI_TIMING_MODE_SDR(x) (FIELD_GET(GENMASK(15, 0), x))
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#define ONFI_TIMING_MODE_NVDDR(x) (FIELD_GET(GENMASK(31, 15), x))
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/* Controller parameter registers */
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#define CNF_GET_NLUNS(x) (FIELD_GET(GENMASK(7, 0), x))
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#define CNF_GET_DEV_TYPE(x) (FIELD_GET(GENMASK(31, 30), x))
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#define CNF_CTRLPARAM_VERSION (0x800)
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#define CNF_CTRLPARAM_FEATURE (0x804)
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#define CNF_CTRLPARAM_MFR_ID (0x808)
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#define CNF_CTRLPARAM_DEV_AREA (0x80C)
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#define CNF_CTRLPARAM_DEV_PARAMS0 (0x810)
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#define CNF_CTRLPARAM_DEV_PARAMS1 (0x814)
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#define CNF_CTRLPARAM_DEV_FEATUERS (0x818)
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#define CNF_CTRLPARAM_DEV_BLOCKS_PLUN (0x81C)
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#define CNF_CTRLPARAM_ONFI_TIMING_0 (0x824)
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#define CNF_CTRLPARAM(_base, _reg) (_base + (CNF_CTRLPARAM_##_reg))
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#define CNF_CMDREG_CTRL_STATUS (0x118)
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#define CNF_CMDREG(_base, _reg) (_base + (CNF_CMDREG_##_reg))
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#define PINSEL(_x) (PINSEL##_x)
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#define PIN(_x) PINSEL(_x)##SEL
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/*Hardware Features Support*/
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#define CNF_HW_NF_16_SUPPORT(x) (FIELD_GET(BIT(29), x))
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#define CNF_HW_NVDDR_SS_SUPPORT(x) (FIELD_GET(BIT(27), x))
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#define CNF_HW_ASYNC_SUPPORT(x) (FIELD_GET(BIT(26), x))
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#define CNF_HW_DMA_DATA_WIDTH_SUPPORT(x) (FIELD_GET(BIT(21), x))
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#define CNF_HW_DMA_ADDR_WIDTH_SUPPORT(x) (FIELD_GET(BIT(20), x))
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#define CNF_HW_DI_PR_SUPPORT(x) (FIELD_GET(BIT(14), x))
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#define CNF_HW_ECC_SUPPORT(x) (FIELD_GET(BIT(17), x))
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#define CNF_HW_RMP_SUPPORT(x) (FIELD_GET(BIT(12), x))
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#define CNF_HW_DI_CRC_SUPPORT(x) (FIELD_GET(BIT(8), x))
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#define CNF_HW_WR_PT_SUPPORT(x) (FIELD_GET(BIT(9), x))
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/* Device types */
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#define CNF_DT_UNKNOWN (0x00)
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#define CNF_DT_ONFI (0x01)
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#define CNF_DT_JEDEC (0x02)
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#define CNF_DT_LEGACY (0x03)
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/* Controller configuration registers */
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#define CNF_CTRLCFG_TRANS_CFG0 (0x400)
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#define CNF_CTRLCFG_TRANS_CFG1 (0x404)
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#define CNF_CTRLCFG_LONG_POLL (0x408)
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#define CNF_CTRLCFG_SHORT_POLL (0x40C)
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#define CNF_CTRLCFG_DEV_STAT (0x410)
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#define CNF_CTRLCFG_DEV_LAYOUT (0x424)
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#define CNF_CTRLCFG_ECC_CFG0 (0x428)
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#define CNF_CTRLCFG_ECC_CFG1 (0x42C)
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#define CNF_CTRLCFG_MULTIPLANE_CFG (0x434)
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#define CNF_CTRLCFG_CACHE_CFG (0x438)
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#define CNF_CTRLCFG_DMA_SETTINGS (0x43C)
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#define CNF_CTRLCFG_FIFO_TLEVEL (0x454)
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#define CNF_CTRLCFG(_base, _reg) (_base + (CNF_CTRLCFG_##_reg))
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/* Data integrity registers */
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#define CNF_DI_PAR_EN (0)
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#define CNF_DI_CRC_EN (1)
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#define CNF_DI_CONTROL (0x700)
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#define CNF_DI_INJECT0 (0x704)
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#define CNF_DI_INJECT1 (0x708)
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#define CNF_DI_ERR_REG_ADDR (0x70C)
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#define CNF_DI_INJECT2 (0x710)
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#define CNF_DI(_base, _reg) (_base + (CNF_DI_##_reg))
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/* Thread idle timeout */
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#define THREAD_IDLE_TIME_OUT 500U
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/* Operation work modes */
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#define CNF_OPR_WORK_MODE_SDR (0)
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#define CNF_OPR_WORK_MODE_NVDDR (1)
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#define CNF_OPR_WORK_MODE_SDR_MASK (GENMASK(1, 0))
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#define CNF_OPR_WORK_MODE_NVDDR_MASK (BIT(0))
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#define ONFI_INTERFACE (0x01)
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#define NV_DDR_TIMING_READ (16)
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/* Interrupt register field offsets */
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#define INTERRUPT_STATUS_REG (0x0114)
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#define THREAD_INTERRUPT_STATUS (0x0138)
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/* Mini controller DLL PHY controller register field offsets */
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#define CNF_DLL_PHY_RST_N (24)
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#define CNF_DLL_PHY_EXT_WR_MODE (17)
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#define CNF_DLL_PHY_EXT_RD_MODE (16)
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#define CNF_MINICTRL_WP_SETTINGS (0x1000)
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#define CNF_MINICTRL_RBN_SETTINGS (0x1004)
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#define CNF_MINICTRL_CMN_SETTINGS (0x1008)
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#define CNF_MINICTRL_SKIP_BYTES_CFG (0x100C)
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#define CNF_MINICTRL_SKIP_BYTES_OFFSET (0x1010)
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#define CNF_MINICTRL_TOGGLE_TIMINGS0 (0x1014)
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#define CNF_MINICTRL_TOGGLE_TIMINGS1 (0x1018)
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#define CNF_MINICTRL_ASYNC_TOGGLE_TIMINGS (0x101C)
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#define CNF_MINICTRL_SYNC_TIMINGS (0x1020)
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#define CNF_MINICTRL_DLL_PHY_CTRL (0x1034)
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#define CNF_MINICTRL(_base, _reg) (_base + (CNF_MINICTRL_##_reg))
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/* Async mode register field offsets */
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#define CNF_ASYNC_TIMINGS_TRH FIELD_PREP(GENMASK(28, 24), 2)
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#define CNF_ASYNC_TIMINGS_TRP FIELD_PREP(GENMASK(20, 16), 4)
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#define CNF_ASYNC_TIMINGS_TWH FIELD_PREP(GENMASK(12, 8), 2)
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#define CNF_ASYNC_TIMINGS_TWP FIELD_PREP(GENMASK(4, 0), 4)
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/* Mini controller common settings register field offsets */
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#define CNF_CMN_SETTINGS_WR_WUP (20)
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#define CNF_CMN_SETTINGS_RD_WUP (16)
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#define CNF_CMN_SETTINGS_DEV16 (8)
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#define CNF_CMN_SETTINGS_OPR (0)
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/* Interrupt status register. */
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#define INTR_STATUS (0x0110)
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#define GINTR_ENABLE (31)
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#define INTERRUPT_DISABLE (0)
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#define INTERRUPT_ENABLE (1)
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/* CDMA Command type descriptor*/
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/* CDMA Command type Erase*/
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#define CNF_CMD_ERASE (0x1000)
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/* CDMA Program Page type */
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#define CNF_CMD_WR (0x2100)
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/* CDMA Read Page type */
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#define CNF_CMD_RD (0x2200)
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#define DMA_MS_SEL (1)
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#define VOL_ID (0)
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#define CDMA_CF_DMA_MASTER (10)
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#define CDMA_CF_DMA_MASTER_SET(x) FIELD_PREP(BIT(CDMA_CF_DMA_MASTER), x)
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#define F_CFLAGS_VOL_ID (4)
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#define F_CFLAGS_VOL_ID_SET(x) FIELD_PREP(GENMASK(7, 4), x)
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#define CDMA_CF_INT (8)
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#define CDMA_CF_INT_SET BIT(CDMA_CF_INT)
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#define COMMON_SET_DEVICE_16BIT (8)
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#define CDNS_READ (0)
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#define CDNS_WRITE (1)
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#define MAX_PAGES_IN_ONE_DSC (8)
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#define CFLAGS_MPTRPC (0)
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#define CFLAGS_MPTRPC_SET FIELD_PREP(BIT(CFLAGS_MPTRPC), 1)
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#define CFLAGS_FPTRPC (1)
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#define CFLAGS_FPTRPC_SET FIELD_PREP(BIT(CFLAGS_FPTRPC), 1)
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#define CFLAGS_CONT (9)
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#define CFLAGS_CONT_SET FIELD_PREP(BIT(CFLAGS_CONT), 1)
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#define CLEAR_ALL_INTERRUPT (0xFFFFFFFF)
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#define ENABLE (1)
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#define DISABLE (0)
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#define DEV_STAT_DEF_VALUE (0x40400000)
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/*Command Resister*/
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#define CDNS_CMD_REG0 (0x00)
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#define CDNS_CMD_REG1 (0x04)
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#define CDNS_CMD_REG2 (0x08)
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#define CDNS_CMD_REG3 (0x0C)
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#define CMD_STATUS_PTR_ADDR (0x10)
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#define CMD_STAT_CMD_STATUS (0x14)
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#define CDNS_CMD_REG4 (0x20)
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/* Cdns Nand Operation Modes*/
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#define CT_CDMA_MODE (0)
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#define CT_PIO_MODE (1)
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#define CT_GENERIC_MODE (3)
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#define OPERATING_MODE_CDMA (0)
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#define OPERATING_MODE_PIO (1)
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#define OPERATING_MODE_GENERIC (2)
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#define THR_STATUS (0x120)
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#define CMD_0_THREAD_POS (24)
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#define CMD_0_THREAD_POS_SET(x) (FIELD_PREP(GENMASK(26, 24), x))
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#define CMD_0_C_MODE (30)
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#define CMD_0_C_MODE_SET(x) (FIELD_PREP(GENMASK(31, 30), x))
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#define CMD_0_VOL_ID_SET(x) (FIELD_PREP(GENMASK(19, 16), x))
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#define PIO_SET_FEA_MODE (0x0100)
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#define SET_FEAT_TIMING_MODE_ADDRESS (0x01)
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/* default thread number*/
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#define NF_TDEF_TRD_NUM (0)
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/* NF device number */
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#define NF_TDEF_DEV_NUM (0)
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#define F_OTE (16)
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#define F_BURST_SEL_SET(x) (FIELD_PREP(GENMASK(7, 0), x))
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/* DMA maximum burst size (0-127)*/
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#define NF_TDEF_BURST_SEL (127)
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#define NF_DMA_SETTING (0x043C)
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#define NF_PRE_FETCH (0x0454)
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#define PRE_FETCH_VALUE (1024/8)
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#define NF_FIFO_TRIGG_LVL_SET(x) (FIELD_PREP(GENMASK(15, 0), x))
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#define NF_DMA_PACKAGE_SIZE_SET(x) (FIELD_PREP(GENMASK(31, 16), x))
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#define NF_FIFO_TRIGG_LVL (0)
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/* BCH correction strength */
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#define NF_TDEF_CORR_STR (0)
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#define F_CSTAT_COMP (15)
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#define F_CSTAT_FAIL (14)
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#define HPNFC_STAT_INPR (0)
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#define HPNFC_STAT_FAIL (2)
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#define HPNFC_STAT_OK (1)
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#define NF_16_ENABLE (1)
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#define NF_16_DISABLE (0)
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/*PIO Mode*/
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#define NF_CMD4_BANK_SET(x) (FIELD_PREP(GENMASK(31, 24), x))
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#define PIO_CMD0_CT_POS (0)
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#define PIO_CMD0_CT_SET(x) (FIELD_PREP(GENMASK(15, 0), x))
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#define PIO_CF_INT (20)
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#define PIO_CF_INT_SET (FIELD_PREP(BIT(PIO_CF_INT), 1))
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#define PIO_CF_DMA_MASTER (21)
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#define PIO_CF_DMA_MASTER_SET(x) (FIELD_PREP(BIT(PIO_CF_DMA_MASTER), x))
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/* Phy registers*/
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#define PHY_DQ_TIMING_REG_OFFSET (0x00002000)
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#define PHY_DQS_TIMING_REG_OFFSET (0x00002004)
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#define PHY_GATE_LPBK_OFFSET (0x00002008)
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#define PHY_DLL_MASTER_OFFSET (0x0000200c)
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#define PHY_CTRL_REG_OFFSET (0x00002080)
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#define PHY_TSEL_REG_OFFSET (0x00002084)
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#define PHY_CTRL_REG_SDR (0x00004040)
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#define PHY_TSEL_REG_SDR (0x00000000)
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#define PHY_DQ_TIMING_REG_SDR (0x00000002)
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#define PHY_DQS_TIMING_REG_SDR (0x00100004)
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#define PHY_GATE_LPBK_CTRL_REG_SDR (0x00D80000)
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#define PHY_DLL_MASTER_CTRL_REG_SDR (0x00800000)
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#define PHY_DLL_SLAVE_CTRL_REG_SDR (0x00000000)
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#define PHY_CTRL_REG_DDR (0x00000000)
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#define PHY_TSEL_REG_DDR (0x00000000)
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#define PHY_DQ_TIMING_REG_DDR (0x00000002)
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#define PHY_DQS_TIMING_REG_DDR (0x00000004)
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#define PHY_GATE_LPBK_CTRL_REG_DDR (0x00380002)
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#define PHY_DLL_MASTER_CTRL_REG_DDR (0x001400fe)
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#define PHY_DLL_SLAVE_CTRL_REG_DDR (0x00003f3f)
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/*SDMA*/
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#define GCMD_TWB_VALUE BIT64(6)
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#define GCMCD_ADDR_SEQ (1)
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#define GCMCD_DATA_SEQ (2)
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#define ERASE_ADDR_SIZE (FIELD_PREP(GENMASK64(13, 11), 3ULL))
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#define GEN_SECTOR_COUNT (1ULL)
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#define GEN_SECTOR_COUNT_SET (FIELD_PREP(GENMASK64(39, 32),\
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GEN_SECTOR_COUNT))
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#define GEN_SECTOR_SIZE (0x100ULL)
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#define GEN_LAST_SECTOR_SIZE_SET(x) (FIELD_PREP(GENMASK64(55, 40), x))
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#define SDMA_TRIGG (21ULL)
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#define SDMA_SIZE_ADDR (0x0440)
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#define SDMA_TRD_NUM_ADDR (0x0444)
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#define SDMA_ADDR0_ADDR (0x044c)
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#define SDMA_ADDR1_ADDR (0x0450)
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#define PAGE_READ_CMD (0x3ULL)
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#define PAGE_WRITE_CMD (0x4ULL)
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#define PAGE_ERASE_CMD (0x6ULL)
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#define PAGE_CMOD_CMD (0x00)
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#define PAGE_MAX_SIZE (4)
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#define PAGE_MAX_BYTES(x) (FIELD_PREP(GENMASK64(13, 11), x))
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#define GEN_CF_INT (20)
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#define GEN_CF_INT_SET(x) (FIELD_PREP(BIT(GEN_CF_INT), x))
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#define GEN_CF_INT_ENABLE (1)
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#define GEN_ADDR_POS (16)
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#define GEN_DIR_SET(x) (FIELD_PREP(BIT64(11), x))
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#define GEN_SECTOR_SET(x) (FIELD_PREP(GENMASK64(31, 16), x))
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#define PAGE_WRITE_10H_CMD (FIELD_PREP(GENMASK64(23, 16), 0x10ULL))
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#define GEN_ADDR_WRITE_DATA(x) (FIELD_PREP(GENMASK64(63, 32), x))
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#define NUM_ONE (1)
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#define U32_MASK_VAL (0xFFFFFFFF)
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#define BIT16_CHECK (16)
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#define IDLE_TIME_OUT (5000U)
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#define ROW_VAL_SET(x, y, z) (FIELD_PREP(GENMASK(x, y), z))
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#define SET_FEAT_ADDR(x) (FIELD_PREP(GENMASK(7, 0), x))
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#define THREAD_VAL(x) (FIELD_PREP(GENMASK(2, 0), x))
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#define INCR_CMD_TYPE(x) (x++)
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#define DECR_CNT_ONE(x) (--x)
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#define GET_INIT_SET_CHECK(x, y) (FIELD_GET(BIT(y), x))
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struct nf_ctrl_version {
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uint32_t ctrl_rev:8;
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uint32_t ctrl_fix:8;
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uint32_t hpnfc_magic_number:16;
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};
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/* Cadence cdma command descriptor*/
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struct cdns_cdma_command_descriptor {
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/* Next descriptor address*/
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uint64_t next_pointer;
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/* Flash address is a 32-bit address comprising of ROW ADDR. */
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uint32_t flash_pointer;
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uint16_t bank_number;
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uint16_t reserved_0;
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/*operation the controller needs to perform*/
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uint16_t command_type;
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uint16_t reserved_1;
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/* Flags for operation of this command. */
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uint16_t command_flags;
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uint16_t reserved_2;
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/* System/host memory address required for data DMA commands. */
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uint64_t memory_pointer;
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/* Status of operation. */
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uint64_t status;
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/* Address pointer to sync buffer location. */
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uint64_t sync_flag_pointer;
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/* Controls the buffer sync mechanism. */
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uint32_t sync_arguments;
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uint32_t reserved_4;
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/* Control data pointer. */
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uint64_t ctrl_data_ptr;
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} __aligned(64);
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/* Row Address */
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union row_address {
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struct {
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uint32_t page_address:7;
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uint32_t block_address:10;
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uint32_t lun_address:3;
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} row_bit_reg;
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uint32_t row_address_raw;
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};
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/* device info structure */
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struct cadence_nand_params {
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uintptr_t nand_base;
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uintptr_t sdma_base;
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uint8_t datarate_mode;
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uint8_t nluns;
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uint16_t page_size;
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uint16_t spare_size;
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uint16_t npages_per_block;
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uint32_t nblocks_per_lun;
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uint32_t block_size;
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uint8_t total_bit_row;
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uint8_t page_size_bit;
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uint8_t block_size_bit;
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uint8_t lun_size_bit;
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size_t page_count;
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unsigned long long device_size;
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#ifdef CONFIG_CDNS_NAND_INTERRUPT_SUPPORT
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struct k_sem interrupt_sem_t;
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#endif
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} __aligned(32);
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/* Global function Api */
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int cdns_nand_init(struct cadence_nand_params *params);
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int cdns_nand_read(struct cadence_nand_params *params, const void *buffer, uint32_t offset,
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uint32_t size);
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int cdns_nand_write(struct cadence_nand_params *params, const void *buffer, uint32_t offset,
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uint32_t len);
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int cdns_nand_erase(struct cadence_nand_params *params, uint32_t offset, uint32_t size);
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#if CONFIG_CDNS_NAND_INTERRUPT_SUPPORT
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void cdns_nand_irq_handler_ll(struct cadence_nand_params *params);
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#endif
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#endif
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