297 lines
6.7 KiB
C
297 lines
6.7 KiB
C
/* adc_qmsi.c - QMSI ADC Sensor Subsystem driver */
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/*
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* Copyright (c) 2016 Intel Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <errno.h>
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#include <init.h>
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#include <nanokernel.h>
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#include <string.h>
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#include <stdlib.h>
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#include <board.h>
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#include <adc.h>
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#include <arch/cpu.h>
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#include <atomic.h>
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#include "qm_ss_isr.h"
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#include "qm_ss_adc.h"
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#include "ss_clk.h"
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enum {
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ADC_STATE_IDLE,
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ADC_STATE_BUSY,
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ADC_STATE_ERROR
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};
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struct adc_info {
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atomic_t state;
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device_sync_call_t sync;
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struct nano_sem sem;
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};
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static void adc_config_irq(void);
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static qm_ss_adc_config_t cfg;
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#if (CONFIG_ADC_QMSI_INTERRUPT)
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static void complete_callback(void *data, int error, qm_ss_adc_status_t status,
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qm_ss_adc_cb_source_t source)
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{
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ARG_UNUSED(status);
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ARG_UNUSED(source);
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struct device *dev = data;
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struct adc_info *info = dev->driver_data;
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if (info) {
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if (error) {
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info->state = ADC_STATE_ERROR;
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}
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device_sync_call_complete(&info->sync);
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}
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}
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#endif
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static void adc_lock(struct adc_info *data)
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{
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nano_sem_take(&data->sem, TICKS_UNLIMITED);
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data->state = ADC_STATE_BUSY;
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}
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static void adc_unlock(struct adc_info *data)
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{
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nano_sem_give(&data->sem);
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data->state = ADC_STATE_IDLE;
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}
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#if (CONFIG_ADC_QMSI_CALIBRATION)
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static void adc_qmsi_ss_enable(struct device *dev)
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{
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struct adc_info *info = dev->driver_data;
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adc_lock(info);
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qm_ss_adc_set_mode(QM_SS_ADC_0, QM_SS_ADC_MODE_NORM_CAL);
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qm_ss_adc_calibrate(QM_SS_ADC_0);
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adc_unlock(info);
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}
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#else
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static void adc_qmsi_ss_enable(struct device *dev)
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{
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struct adc_info *info = dev->driver_data;
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adc_lock(info);
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qm_ss_adc_set_mode(QM_SS_ADC_0, QM_SS_ADC_MODE_NORM_NO_CAL);
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adc_unlock(info);
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}
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#endif /* CONFIG_ADC_QMSI_CALIBRATION */
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static void adc_qmsi_ss_disable(struct device *dev)
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{
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struct adc_info *info = dev->driver_data;
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adc_lock(info);
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/* Go to deep sleep */
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qm_ss_adc_set_mode(QM_SS_ADC_0, QM_SS_ADC_MODE_DEEP_PWR_DOWN);
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adc_unlock(info);
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}
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#if (CONFIG_ADC_QMSI_POLL)
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static int adc_qmsi_ss_read(struct device *dev, struct adc_seq_table *seq_tbl)
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{
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int i, ret = 0;
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qm_ss_adc_xfer_t xfer;
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qm_ss_adc_status_t status;
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struct adc_info *info = dev->driver_data;
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for (i = 0; i < seq_tbl->num_entries; i++) {
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xfer.ch = (qm_ss_adc_channel_t *)&seq_tbl->entries[i].channel_id;
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/* Just one channel at the time using the Zephyr sequence table
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*/
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xfer.ch_len = 1;
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xfer.samples = (qm_ss_adc_sample_t *)seq_tbl->entries[i].buffer;
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/* buffer length (bytes) the number of samples, the QMSI Driver
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* does not allow more than QM_ADC_FIFO_LEN samples at the time
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* in polling mode, if that happens, the qm_adc_convert api will
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* return with an error
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*/
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xfer.samples_len =
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(seq_tbl->entries[i].buffer_length)/sizeof(qm_ss_adc_sample_t);
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xfer.callback = NULL;
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xfer.callback_data = NULL;
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cfg.window = seq_tbl->entries[i].sampling_delay;
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adc_lock(info);
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if (qm_ss_adc_set_config(QM_SS_ADC_0, &cfg) != 0) {
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ret = -EINVAL;
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adc_unlock(info);
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break;
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}
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/* Run the conversion, here the function will poll for the
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* samples. The function will constantly read the status
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* register to check if the number of samples required has been
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* captured
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*/
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if (qm_ss_adc_convert(QM_SS_ADC_0, &xfer, &status) != 0) {
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ret = -EIO;
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adc_unlock(info);
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break;
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}
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/* Successful Analog to Digital conversion */
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adc_unlock(info);
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}
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return ret;
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}
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#else
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static int adc_qmsi_ss_read(struct device *dev, struct adc_seq_table *seq_tbl)
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{
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int i, ret = 0;
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qm_ss_adc_xfer_t xfer;
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struct adc_info *info = dev->driver_data;
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for (i = 0; i < seq_tbl->num_entries; i++) {
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xfer.ch = (qm_ss_adc_channel_t *)&seq_tbl->entries[i].channel_id;
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/* Just one channel at the time using the Zephyr sequence table */
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xfer.ch_len = 1;
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xfer.samples =
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(qm_ss_adc_sample_t *)seq_tbl->entries[i].buffer;
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xfer.samples_len =
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(seq_tbl->entries[i].buffer_length)/sizeof(qm_ss_adc_sample_t);
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xfer.callback = complete_callback;
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xfer.callback_data = dev;
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cfg.window = seq_tbl->entries[i].sampling_delay;
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adc_lock(info);
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if (qm_ss_adc_set_config(QM_SS_ADC_0, &cfg) != 0) {
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ret = -EINVAL;
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adc_unlock(info);
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break;
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}
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/* This is the interrupt driven API, will generate and interrupt and
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* call the complete_callback function once the samples have been
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* obtained
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*/
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if (qm_ss_adc_irq_convert(QM_SS_ADC_0, &xfer) != 0) {
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ret = -EIO;
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adc_unlock(info);
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break;
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}
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/* Wait for the interrupt to finish */
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device_sync_call_wait(&info->sync);
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if (info->state == ADC_STATE_ERROR) {
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ret = -EIO;
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adc_unlock(info);
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break;
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}
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/* Successful Analog to Digital conversion */
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adc_unlock(info);
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}
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return ret;
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}
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#endif /* CONFIG_ADC_QMSI_POLL */
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void adc_qmsi_ss_rx_isr(void *arg)
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{
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ARG_UNUSED(arg);
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qm_ss_adc_0_isr(NULL);
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}
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void adc_qmsi_ss_err_isr(void *arg)
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{
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ARG_UNUSED(arg);
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qm_ss_adc_0_err_isr(NULL);
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}
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static struct adc_driver_api api_funcs = {
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.enable = adc_qmsi_ss_enable,
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.disable = adc_qmsi_ss_disable,
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.read = adc_qmsi_ss_read,
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};
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int adc_qmsi_ss_init(struct device *dev)
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{
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struct adc_info *info = dev->driver_data;
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dev->driver_api = &api_funcs;
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/* Set up config */
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/* Clock cycles between the start of each sample */
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cfg.window = CONFIG_ADC_QMSI_SERIAL_DELAY;
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cfg.resolution = CONFIG_ADC_QMSI_SAMPLE_WIDTH;
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qm_ss_adc_set_config(QM_SS_ADC_0, &cfg);
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ss_clk_adc_enable();
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ss_clk_adc_set_div(CONFIG_ADC_QMSI_CLOCK_RATIO);
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device_sync_call_init(&info->sync);
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nano_sem_init(&info->sem);
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nano_sem_give(&info->sem);
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info->state = ADC_STATE_IDLE;
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adc_config_irq();
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return 0;
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}
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struct adc_info adc_info_dev;
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DEVICE_INIT(adc_qmsi_ss, CONFIG_ADC_0_NAME, &adc_qmsi_ss_init,
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&adc_info_dev, NULL,
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SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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static void adc_config_irq(void)
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{
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uint32_t *scss_intmask;
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IRQ_CONNECT(IRQ_ADC_IRQ, CONFIG_ADC_0_IRQ_PRI,
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adc_qmsi_ss_rx_isr, DEVICE_GET(adc_qmsi_ss), 0);
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irq_enable(IRQ_ADC_IRQ);
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IRQ_CONNECT(IRQ_ADC_ERR, CONFIG_ADC_0_IRQ_PRI,
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adc_qmsi_ss_err_isr, DEVICE_GET(adc_qmsi_ss), 0);
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irq_enable(IRQ_ADC_ERR);
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scss_intmask = (uint32_t *)&QM_SCSS_INT->int_ss_adc_err_mask;
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*scss_intmask &= ~BIT(8);
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scss_intmask = (uint32_t *)&QM_SCSS_INT->int_ss_adc_irq_mask;
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*scss_intmask &= ~BIT(8);
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}
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