504 lines
14 KiB
Plaintext
504 lines
14 KiB
Plaintext
/*
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* Copyright (c) 2020 ITE Corporation. All Rights Reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/linker/sections.h>
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#include <zephyr/linker/devicetree_regions.h>
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#include <zephyr/linker/linker-defs.h>
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#include <zephyr/linker/linker-tool.h>
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#ifdef CONFIG_XIP
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#define ROMABLE_REGION ROM
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#else
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#define ROMABLE_REGION RAM
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#endif
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#define RAMABLE_REGION RAM
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#define _EXCEPTION_SECTION_NAME exceptions
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#define _RESET_SECTION_NAME reset
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#ifdef CONFIG_XIP
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#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)
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#ifdef CONFIG_FLASH_LOAD_OFFSET
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#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + \
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CONFIG_FLASH_LOAD_OFFSET)
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#else /* !CONFIG_FLASH_LOAD_OFFSET */
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#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
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#endif /* CONFIG_FLASH_LOAD_OFFSET */
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#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
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#elif DT_NODE_HAS_COMPAT(DT_CHOSEN(zephyr_flash), jedec_spi_nor)
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/* For jedec,spi-nor we expect the spi controller to memory map the flash
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* and for that mapping to be the second register property of the spi
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* controller.
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*/
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#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))
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#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)
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#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)
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#endif
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#else /* CONFIG_XIP */
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#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS
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#define ROM_SIZE KB(CONFIG_SRAM_SIZE)
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#endif /* CONFIG_XIP */
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#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS
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#define RAM_SIZE KB(CONFIG_SRAM_SIZE)
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#ifdef CONFIG_RISCV_PMP
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#define MPU_MIN_SIZE 4
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#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE);
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#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)
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#define MPU_ALIGN(region_size) \
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. = ALIGN(MPU_MIN_SIZE); \
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. = ALIGN( 1 << LOG2CEIL(region_size))
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#else
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#define MPU_ALIGN(region_size) \
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. = ALIGN(MPU_MIN_SIZE)
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#endif
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#else
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#define MPU_MIN_SIZE_ALIGN
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#define MPU_ALIGN(region_size) . = ALIGN(4)
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#endif
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#include <zephyr/linker/linker-devnull.h>
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MEMORY
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{
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#ifdef CONFIG_XIP
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ROM (rx) : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE
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#endif
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RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE
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#if defined(CONFIG_LINKER_DEVNULL_MEMORY)
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DEVNULL_ROM (rx) : ORIGIN = DEVNULL_ADDR, LENGTH = DEVNULL_SIZE
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#endif
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LINKER_DT_REGIONS()
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/* Used by and documented in include/linker/intlist.ld */
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IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
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}
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ENTRY(CONFIG_KERNEL_ENTRY)
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SECTIONS
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{
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#include <zephyr/linker/rel-sections.ld>
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#ifdef CONFIG_LLEXT
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#include <zephyr/linker/llext-sections.ld>
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#endif
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/*
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* The .plt and .iplt are here according to
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* 'riscv32-zephyr-elf-ld --verbose', before text section.
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*/
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SECTION_PROLOGUE(.plt,,)
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{
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*(.plt)
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}
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SECTION_PROLOGUE(.iplt,,)
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{
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*(.iplt)
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}
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GROUP_START(ROMABLE_REGION)
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__rom_region_start = ROM_BASE;
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SECTION_PROLOGUE(rom_start,,)
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{
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. = ALIGN(16);
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/* Located in generated directory. This file is populated by calling
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* zephyr_linker_sources(ROM_START ...).
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*/
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#include <snippets-rom-start.ld>
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} GROUP_LINK_IN(ROMABLE_REGION)
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#ifdef CONFIG_CODE_DATA_RELOCATION
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#include <linker_relocate.ld>
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#endif
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SECTION_PROLOGUE(_RESET_SECTION_NAME,,)
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{
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KEEP(*(.reset.*))
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} GROUP_LINK_IN(ROMABLE_REGION)
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#ifdef CONFIG_SOC_IT8XXX2_JTAG_DEBUG_INTERFACE
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#define JTAG_DEBUG_RESERVED_ADDR_START 0x80000800
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#define JTAG_DEBUG_RESERVED_ADDR_END 0x800008FF
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/* The CPU address from 0x80000800 to 0x800008FF is reserved for JTAG
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* debug usage. */
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SECTION_PROLOGUE(jtag_dbg,,)
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{
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__jtag_dbg_pad_start = ABSOLUTE(.);
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ASSERT((__jtag_dbg_pad_start < JTAG_DEBUG_RESERVED_ADDR_START),
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"The start address of jtag debug section is incorrect.");
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__jtag_dbg_pad_size = JTAG_DEBUG_RESERVED_ADDR_END - __jtag_dbg_pad_start;
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. = . + __jtag_dbg_pad_size;
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__jtag_dbg_pad_end = ABSOLUTE(.);
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ASSERT((__jtag_dbg_pad_end == JTAG_DEBUG_RESERVED_ADDR_END),
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"The end address of jtag debug section is incorrect.");
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} GROUP_LINK_IN(ROMABLE_REGION)
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#endif
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#ifndef CONFIG_SOC_IT8XXX2_EXCEPTIONS_IN_RAM
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SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)
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{
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KEEP(*(".exception.entry.*"))
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*(".exception.other.*")
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} GROUP_LINK_IN(ROMABLE_REGION)
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#endif
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SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
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{
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. = ALIGN(4);
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KEEP(*(.openocd_debug))
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KEEP(*(".openocd_debug.*"))
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__text_region_start = .;
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#ifndef CONFIG_SOC_IT8XXX2_LIBRARY_TO_RAM
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*(.text)
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*(".text.*")
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#endif
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#ifdef CONFIG_SOC_IT8XXX2_LIBRARY_TO_RAM
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*(EXCLUDE_FILE (
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#endif
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#ifdef CONFIG_SOC_IT8XXX2_SERIAL_IN_RAM
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*libdrivers__serial.a:*
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#endif
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#ifdef CONFIG_SOC_IT8XXX2_KERNEL_IN_RAM
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*libkernel.a:*
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#endif
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#ifdef CONFIG_SOC_IT8XXX2_ZEPHYR_IN_RAM
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*libzephyr.a:*
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#endif
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#ifdef CONFIG_SOC_IT8XXX2_LIBRARY_TO_RAM
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)
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.text
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)
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#endif
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#ifdef CONFIG_SOC_IT8XXX2_LIBRARY_TO_RAM
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*(EXCLUDE_FILE (
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#endif
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#ifdef CONFIG_SOC_IT8XXX2_SERIAL_IN_RAM
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*libdrivers__serial.a:*
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#endif
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#ifdef CONFIG_SOC_IT8XXX2_KERNEL_IN_RAM
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*libkernel.a:*
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#endif
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#ifdef CONFIG_SOC_IT8XXX2_ZEPHYR_IN_RAM
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*libzephyr.a:*
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#endif
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#ifdef CONFIG_SOC_IT8XXX2_LIBRARY_TO_RAM
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)
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.text.*
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)
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#endif
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*(.gnu.linkonce.t.*)
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#include <zephyr/linker/kobject-text.ld>
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/* IT8xxx2 requires memory mappings be configured for execution
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* out of RAM, which refer to contiguous blocks of RAM. Place
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* all relevant sections together to minimize RAM waste. */
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. = ALIGN(0x1000);
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/* Mapping base address must be 4k-aligned */
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__ilm_flash_start = .;
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#ifdef CONFIG_SOC_IT8XXX2_SHA256_HW_ACCELERATE
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/* Pad to match allocation of block in RAM,
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* maintaining code alignment against ILM */
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__sha256_pad_block_start = .;
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. = . + CONFIG_SOC_IT8XXX2_SHA256_BLOCK_SIZE;
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#endif
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/* Specially-tagged functions in SoC sources */
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KEEP(*(.__ram_code))
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*(.__ram_code.*)
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#ifdef CONFIG_SOC_IT8XXX2_EXCEPTIONS_IN_RAM
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KEEP(*(".exception.entry.*"))
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*(".exception.other.*")
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#endif
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#ifdef CONFIG_SOC_IT8XXX2_SERIAL_IN_RAM
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*libdrivers__serial.a:*(.text .text.*)
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*libdrivers__serial.a:*(.rodata .rodata.*)
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*libdrivers__serial.a:*(.srodata .srodata.*)
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#endif
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#ifdef CONFIG_SOC_IT8XXX2_KERNEL_IN_RAM
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*libkernel.a:*(.text .text.*)
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*libkernel.a:*(.rodata .rodata.*)
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*libkernel.a:*(.srodata .srodata.*)
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#endif
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#ifdef CONFIG_SOC_IT8XXX2_ZEPHYR_IN_RAM
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*libzephyr.a:*(.text .text.*)
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*libzephyr.a:*(.rodata .rodata.*)
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*libzephyr.a:*(.srodata .srodata.*)
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#endif
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__ilm_flash_end = .;
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/* ILM mapping is always a multiple of 4k size; ensure following
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* sections won't incorrectly redirect to RAM. */
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. = ALIGN(0x1000);
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} GROUP_LINK_IN(ROMABLE_REGION)
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__text_region_end = .;
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__rodata_region_start = .;
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#include <zephyr/linker/common-rom.ld>
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/* Located in generated directory. This file is populated by calling
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* zephyr_linker_sources(ROM_SECTIONS ...). Useful for grouping iterable RO structs.
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*/
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#include <snippets-rom-sections.ld>
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#include <zephyr/linker/thread-local-storage.ld>
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SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
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{
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. = ALIGN(4);
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*(.srodata)
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*(".srodata.*")
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*(.rodata)
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*(".rodata.*")
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*(.gnu.linkonce.r.*)
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*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
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/* Located in generated directory. This file is populated by the
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* zephyr_linker_sources() Cmake function.
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*/
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#include <snippets-rodata.ld>
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#include <zephyr/linker/kobject-rom.ld>
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. = ALIGN(4);
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} GROUP_LINK_IN(ROMABLE_REGION)
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#include <zephyr/linker/cplusplus-rom.ld>
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__rodata_region_end = .;
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/* For non-XIP system, __rom_region_end symbol should be set to
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* the end of common ROMABLE_REGIONs (text and rodata) instead of
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* the linker script end, so it wouldn't mistakenly contain
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* RAMABLE_REGION in it.
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*/
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#ifndef CONFIG_XIP
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#ifdef CONFIG_RISCV_PMP
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SECTION_PROLOGUE(rom_mpu_padding,,)
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{
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MPU_ALIGN(__rodata_region_end - __rom_region_start);
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#ifdef CONFIG_QEMU_TARGET
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/*
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* QEMU doesn't vet each instruction fetch individually.
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* Instead, it grabs a whole page and perform dynamic
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* transation on it in a batch. It therefore validates
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* PMP permissions using page-sized and -aligned chunks.
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*/
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. = ALIGN(0x1000);
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#endif
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} GROUP_LINK_IN(ROMABLE_REGION)
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#endif /* CONFIG_RISCV_PMP */
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__rom_region_end = .;
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__rom_region_size = __rom_region_end - __rom_region_start;
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#endif /* CONFIG_XIP */
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GROUP_END(ROMABLE_REGION)
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GROUP_START(RAMABLE_REGION)
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. = RAM_BASE;
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/* Claim RAM for ILM mappings; must be 4k-aligned and each mapping is 4k in
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* size, but mapped regions can still be accessed as data so don't need to be
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* padded out to 4k size. This doesn't load any sections because code in ILM
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* is still accessed at its VMA in ROM. */
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SECTION_PROLOGUE(ilm_ram,(NOLOAD),ALIGN(0x1000))
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{
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__ilm_ram_start = .;
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#ifdef CONFIG_SOC_IT8XXX2_SHA256_HW_ACCELERATE
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__sha256_ram_block_start = .;
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KEEP(*(.__sha256_ram_block))
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__sha256_ram_block_size = \
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ABSOLUTE(. - __sha256_ram_block_start);
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__sha256_ram_block_end = .;
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ASSERT((__sha256_ram_block_size == CONFIG_SOC_IT8XXX2_SHA256_BLOCK_SIZE), \
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"Not compatible ram size for HW sha256 module");
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ASSERT((__sha256_ram_block_end < (RAM_BASE + 0x1000)), \
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"sha256 ram block must in SRAM first 4kbytes");
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ASSERT(((ABSOLUTE(__sha256_ram_block_start) & 0xfff) == \
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(ABSOLUTE(__sha256_pad_block_start) & 0xfff)), \
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"sha256 ram block needs the same offset with sha256 rom block");
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#else
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__sha256_ram_block_size = 0;
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#endif
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. += __ilm_flash_end - __ilm_flash_start - __sha256_ram_block_size;
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__ilm_ram_end = .;
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} GROUP_LINK_IN(RAMABLE_REGION)
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_image_ram_start = .;
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/* Located in generated directory. This file is populated by the
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* zephyr_linker_sources() Cmake function.
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*/
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#include <snippets-ram-sections.ld>
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#if defined(CONFIG_USERSPACE)
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#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN
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#define SMEM_PARTITION_ALIGN MPU_ALIGN
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#include <app_smem.ld>
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_app_smem_size = _app_smem_end - _app_smem_start;
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_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);
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#endif /* CONFIG_USERSPACE */
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SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
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{
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MPU_MIN_SIZE_ALIGN
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/*
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* For performance, BSS section is assumed to be 4 byte aligned and
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* a multiple of 4 bytes
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*/
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. = ALIGN(4);
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__bss_start = .;
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__kernel_ram_start = .;
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*(.sbss)
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*(".sbss.*")
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*(.bss)
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*(".bss.*")
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COMMON_SYMBOLS
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#ifdef CONFIG_CODE_DATA_RELOCATION
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#include <linker_sram_bss_relocate.ld>
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#endif
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/*
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* As memory is cleared in words only, it is simpler to ensure the BSS
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* section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
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*/
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__bss_end = ALIGN(4);
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} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
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#include <zephyr/linker/common-noinit.ld>
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SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)
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{
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. = ALIGN(4);
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/* _image_ram_start = .; */
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__data_region_start = .;
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__data_start = .;
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*(.data)
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*(".data.*")
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#ifdef CONFIG_RISCV_GP
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/*
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* RISC-V architecture has 12-bit signed immediate offsets in the
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* instructions. If we can put the most commonly accessed globals
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* in a special 4K span of memory addressed by the GP register, then
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* we can access those values in a single instruction, saving both
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* codespace and runtime.
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*
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* Since these immediate offsets are signed, place gp 0x800 past the
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* beginning of .sdata so that we can use both positive and negative
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* offsets.
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*/
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. = ALIGN(8);
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PROVIDE (__global_pointer$ = . + 0x800);
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#endif
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*(.sdata .sdata.* .gnu.linkonce.s.*)
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/* Located in generated directory. This file is populated by the
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* zephyr_linker_sources() Cmake function.
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*/
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#include <snippets-rwdata.ld>
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#ifdef CONFIG_CODE_DATA_RELOCATION
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#include <linker_sram_data_relocate.ld>
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#endif
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__data_end = .;
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} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
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__data_size = __data_end - __data_start;
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__data_load_start = LOADADDR(_DATA_SECTION_NAME);
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__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);
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#include <zephyr/linker/common-ram.ld>
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#include <zephyr/linker/kobject-data.ld>
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#include <zephyr/linker/cplusplus-ram.ld>
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/* Located in generated directory. This file is populated by the
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* zephyr_linker_sources() Cmake function.
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*/
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#include <snippets-data-sections.ld>
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__data_region_end = .;
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SECTION_DATA_PROLOGUE(.h2ram_pool,(NOLOAD),)
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{
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/*
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* Since __sha256_ram_block section must in the first 4KB,
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* h2ram_pool section is no longer included first inside the
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* RAMABLE_REGION.
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* Append h2ram_pool section at the end of used memory, so gap
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* due to alignment is still available for newly added variables
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*/
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. = ALIGN(0x1000);
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_h2ram_pool_start = .;
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KEEP(*(.h2ram_pool))
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_h2ram_pool_end = .;
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} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
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_h2ram_pool_size = ABSOLUTE(_h2ram_pool_end - _h2ram_pool_start);
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__kernel_ram_end = .;
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__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;
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/* Located in generated directory. This file is populated by the
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* zephyr_linker_sources() Cmake function.
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*/
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#include <snippets-sections.ld>
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#define LAST_RAM_ALIGN MPU_MIN_SIZE_ALIGN
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#include <zephyr/linker/ram-end.ld>
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GROUP_END(RAMABLE_REGION)
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#include <zephyr/linker/debug-sections.ld>
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/DISCARD/ : { *(.note.GNU-stack) }
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SECTION_PROLOGUE(.riscv.attributes, 0,)
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{
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KEEP(*(.riscv.attributes))
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KEEP(*(.gnu.attributes))
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}
|
|
|
|
/* Sections generated from 'zephyr,memory-region' nodes */
|
|
LINKER_DT_SECTIONS()
|
|
|
|
/* Because ROMABLE_REGION != RAMABLE_REGION in XIP-system, it is valid
|
|
* to set __rom_region_end symbol at the end of linker script and
|
|
* doesn't mistakenly contain the RAMABLE_REGION in it.
|
|
*/
|
|
#ifdef CONFIG_XIP
|
|
/* Must be last in romable region */
|
|
SECTION_PROLOGUE(.last_section,(NOLOAD),)
|
|
{
|
|
} GROUP_LINK_IN(ROMABLE_REGION)
|
|
|
|
/* To provide the image size as a const expression,
|
|
* calculate this value here. */
|
|
__rom_region_end = LOADADDR(.last_section);
|
|
__rom_region_size = __rom_region_end - __rom_region_start;
|
|
#endif
|
|
|
|
}
|