108 lines
2.6 KiB
Plaintext
108 lines
2.6 KiB
Plaintext
# Kconfig - XTENSA architecture configuration options
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#
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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choice
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prompt "XTENSA core Selection"
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depends on XTENSA
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source "arch/xtensa/soc/*/Kconfig.soc"
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endchoice
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menu "XTENSA Options"
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depends on XTENSA
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config ARCH
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default "xtensa"
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config SIMULATOR_XTENSA
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bool
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prompt "Simulator Configuration"
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default n
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help
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Specify if the board configuration should be treated as a simulator.
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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int
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prompt "Hardware clock cycles per second, 2000000 for ISS"
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default 2000000
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range 1000000 1000000000
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help
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This option specifies hardware clock.
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config XTENSA_NO_IPC
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bool "Core has no IPC support"
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select ATOMIC_OPERATIONS_C
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default n
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help
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Uncheck this if you core does not implement "SCOMPARE1" register and "s32c1i"
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instruction.
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config SW_ISR_TABLE
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bool
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prompt "Enable software interrupt handler table"
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default y
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help
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Enable an interrupt handler table implemented in software. This
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table, unlike ISRs connected directly in the vector table, allow
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a parameter to be passed to the interrupt handlers. Also, invoking
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the exception/interrupt exit stub is automatically done.
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This has to be enabled for dynamically connecting interrupt handlers
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at runtime (SW_ISR_TABLE_DYNAMIC).
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config IRQ_OFFLOAD
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bool "Enable IRQ offload"
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default n
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help
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Enable irq_offload() API which allows functions to be synchronously
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run in interrupt context. Uses one entry in the IDT. Mainly useful
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for test cases.
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config SW_ISR_TABLE_DYNAMIC
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bool
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prompt "Allow installing interrupt handlers at runtime"
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depends on SW_ISR_TABLE
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default n
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help
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This option enables irq_connect_dynamic(). It moves the ISR table to
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SRAM so that it is writable. This has the side-effect of removing
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write-protection on the ISR table.
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config XTENSA_RESET_VECTOR
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bool
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prompt "Build reset vector code"
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default y
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help
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This option controls whether the initial reset vector code is built.
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This is always needed for the simulator. Real boards may already
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implement this in boot ROM.
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config XTENSA_USE_CORE_CRT1
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bool
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prompt "Use crt1.S from core"
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default y
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help
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SoC or boards might define their own __start by setting this setting
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to false.
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menu "Specific core configuration"
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config IRQ_OFFLOAD_INTNUM
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int
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prompt "IRQ offload SW interrupt index"
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help
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The index of the software interrupt to be used for IRQ offload.
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Please note that in order for IRQ offload to work correctly the selected
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interrupt shall have its priority shall not exceed XCHAL_EXCM_LEVEL.
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config TOOLCHAIN_VARIANT
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string
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default RG-2016.4-linux
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source "arch/xtensa/soc/*/Kconfig"
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endmenu
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endmenu
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