zephyr/arch/riscv32
Jean-Paul Etienne 34862656b9 riscv32: fixed context restore upon exiting ISR
By now, t0 register restored value is overwritten
by mepc and mstatus values prior to returning from ISR.

Fixed by restoring mstatus and mepc registers before
restoring the caller-saved registers.

As t0 is a temporary register within the riscv ABI,
this issue was unnoticed for most applications, except
for computation intensive apps, like crypto tests.

Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-06-30 06:31:51 -04:00
..
core riscv32: fixed context restore upon exiting ISR 2017-06-30 06:31:51 -04:00
include linker: move all linker headers to include/linker 2017-06-18 09:24:04 -05:00
soc linker: move all linker headers to include/linker 2017-06-18 09:24:04 -05:00
Kbuild riscv32: added the riscv-privilege SOC_FAMILY 2017-03-20 23:19:35 +00:00
Kconfig riscv32: enable gen_isr_tables mechanism 2017-02-15 04:49:17 +00:00
Makefile riscv32: added the riscv-privilege SOC_FAMILY 2017-03-20 23:19:35 +00:00
defconfig