154 lines
5.6 KiB
C
154 lines
5.6 KiB
C
/*
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* Copyright (c) 2016 Cadence Design Systems, Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY
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*
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* This header contains definitions and macros for use primarily by Xtensa
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* RTOS assembly coded source files. It includes and uses the Xtensa hardware
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* abstraction layer (HAL) to deal with config specifics. It may also be
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* included in C source files.
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*
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* User may edit to modify timer selection and to specify clock frequency and
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* tick duration to match timer interrupt to the real-time tick duration.
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*
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* If the RTOS has no timer interrupt, then there is no tick timer and the
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* clock frequency is irrelevant, so all of these macros are left undefined
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* and the Xtensa core configuration need not have a timer.
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*/
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#ifndef XTENSA_TIMER_H
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#define XTENSA_TIMER_H
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#ifdef __ASSEMBLER__
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#include <xtensa/coreasm.h>
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#endif
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#include <xtensa/corebits.h>
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#include <xtensa/config/system.h>
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#include "xtensa_rtos.h" /* in case this wasn't included directly */
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#if CONFIG_XTENSA_INTERNAL_TIMER || (CONFIG_XTENSA_TIMER_IRQ < 0)
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/*
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* Select timer to use for periodic tick, and determine its interrupt number
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* and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
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* in which case its validity is checked (it must exist in this core and must
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* not be on a high priority interrupt - an error will be reported in invalid).
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* Otherwise select the first low or medium priority interrupt timer available.
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*/
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#if XCHAL_NUM_TIMERS == 0
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#error "This Xtensa configuration is unsupported, it has no timers."
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#endif /* XCHAL_NUM_TIMERS */
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#ifndef XT_TIMER_INDEX
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#if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
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#if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL
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#undef XT_TIMER_INDEX
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#define XT_TIMER_INDEX 3
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#endif
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#endif
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#if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
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#if XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
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#undef XT_TIMER_INDEX
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#define XT_TIMER_INDEX 2
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#endif
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#endif
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#if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
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#if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
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#undef XT_TIMER_INDEX
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#define XT_TIMER_INDEX 1
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#endif
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#endif
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#if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
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#if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
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#undef XT_TIMER_INDEX
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#define XT_TIMER_INDEX 0
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#endif
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#endif
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#endif
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#ifndef XT_TIMER_INDEX
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#error "There is no suitable timer in this Xtensa configuration."
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#endif
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#define XT_CCOMPARE ((CCOMPARE) + (XT_TIMER_INDEX))
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#define XT_TIMER_INTNUM XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX)
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#if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED
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#error "The timer selected by XT_TIMER_INDEX does not exist in this core."
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#endif
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#else /* Case of an external timer which is not emulated by internal timer */
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#define XT_TIMER_INTNUM CONFIG_XTENSA_TIMER_IRQ
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#endif /* CONFIG_XTENSA_INTERNAL_TIMER || (CONFIG_XTENSA_TIMER_IRQ < 0) */
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#if CONFIG_XTENSA_INTERNAL_TIMER
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#define XT_TIMER_INTPRI XCHAL_INT_LEVEL(XT_TIMER_INTNUM)
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#else
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#define XT_TIMER_INTPRI CONFIG_XTENSA_TIMER_IRQ_PRIORITY
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#endif /* CONFIG_XTENSA_INTERNAL_TIMER */
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#if XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL
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#error "The timer interrupt cannot be high priority (use medium or low)."
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#endif
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#define XT_TIMER_INTEN (1 << (XT_TIMER_INTNUM))
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/*
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* Set processor clock frequency, used to determine clock divisor for timer
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* tick. User should BE SURE TO ADJUST THIS for the Xtensa platform being
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* used. If using a supported board via the board-independent API defined in
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* xtbsp.h, this may be left undefined and frequency and tick divisor will be
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* computed and cached during run-time initialization.
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*
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* NOTE ON SIMULATOR: Under the Xtensa instruction set simulator, the frequency
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* can only be estimated because it depends on the speed of the host and the
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* version of the simulator. Also because it runs much slower than hardware,
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* it is not possible to achieve real-time performance for most applications
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* under the simulator. A frequency too low does not allow enough time between
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* timer interrupts, starving threads. To obtain a more convenient but
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* non-real-time tick duration on the simulator, compile with xt-xcc option
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* "-DXT_SIMULATOR". Adjust this frequency to taste (it's not real-time
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* anyway!).
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*/
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#if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ)
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#define XT_CLOCK_FREQ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
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#endif
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#if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD)
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#error "XT_CLOCK_FREQ must be defined for the target platform."
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#endif
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/*
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* Default number of timer "ticks" per second (default 100 for 10ms tick).
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* RTOS may define this in its own way (if applicable) in xtensa_rtos.h.
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* User may redefine this to an optimal value for the application, either by
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* editing this here or in xtensa_rtos.h, or compiling with xt-xcc option
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* "-DXT_TICK_PER_SEC=<value>" where <value> is a suitable number.
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*/
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#ifndef XT_TICK_PER_SEC
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#if CONFIG_TICKLESS_KERNEL
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#define XT_TICK_PER_SEC 1000 /* In tickless kernel 1TICK = 1msec */
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#else
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#define XT_TICK_PER_SEC CONFIG_SYS_CLOCK_TICKS_PER_SEC
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#endif /* CONFIG_TICKLESS_KERNEL */
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#endif /* XT_TICK_PER_SEC */
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/*
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* Derivation of clock divisor for timer tick and interrupt (one per tick).
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*/
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#ifdef XT_CLOCK_FREQ
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#define XT_TICK_DIVISOR (XT_CLOCK_FREQ / XT_TICK_PER_SEC)
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#endif
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#if CONFIG_XTENSA_INTERNAL_TIMER || (CONFIG_XTENSA_TIMER_IRQ < 0)
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#ifndef __ASSEMBLER__
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extern unsigned int _xt_tick_divisor;
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extern void _xt_tick_divisor_init(void);
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#endif
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#endif // Internal/External timer
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#endif /* XTENSA_TIMER_H */
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