415 lines
11 KiB
ArmAsm
415 lines
11 KiB
ArmAsm
/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Thread context switching for ARM Cortex-M
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*
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* This module implements the routines necessary for thread context switching
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* on ARM Cortex-M CPUs.
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*/
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#include <kernel_structs.h>
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#include <offsets_short.h>
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#include <toolchain.h>
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#include <arch/cpu.h>
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_ASM_FILE_PROLOGUE
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GTEXT(__swap)
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GTEXT(__svc)
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GTEXT(__pendsv)
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GTEXT(_do_kernel_oops)
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GDATA(_k_neg_eagain)
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GDATA(_kernel)
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/**
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*
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* @brief PendSV exception handler, handling context switches
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*
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* The PendSV exception is the only execution context in the system that can
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* perform context switching. When an execution context finds out it has to
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* switch contexts, it pends the PendSV exception.
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*
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* When PendSV is pended, the decision that a context switch must happen has
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* already been taken. In other words, when __pendsv() runs, we *know* we have
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* to swap *something*.
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*/
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SECTION_FUNC(TEXT, __pendsv)
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#ifdef CONFIG_KERNEL_EVENT_LOGGER_CONTEXT_SWITCH
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/* Register the context switch */
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push {lr}
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bl _sys_k_event_logger_context_switch
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#if defined(CONFIG_ARMV6_M)
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pop {r0}
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mov lr, r0
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#else
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pop {lr}
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#endif /* CONFIG_ARMV6_M */
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#endif /* CONFIG_KERNEL_EVENT_LOGGER_CONTEXT_SWITCH */
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/* load _kernel into r1 and current k_thread into r2 */
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ldr r1, =_kernel
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ldr r2, [r1, #_kernel_offset_to_current]
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/* addr of callee-saved regs in thread in r0 */
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ldr r0, =_thread_offset_to_callee_saved
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add r0, r2
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/* save callee-saved + psp in thread */
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mrs ip, PSP
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#if defined(CONFIG_ARMV6_M)
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/* Store current r4-r7 */
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stmea r0!, {r4-r7}
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/* copy r8-r12 into r3-r7 */
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mov r3, r8
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mov r4, r9
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mov r5, r10
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mov r6, r11
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mov r7, ip
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/* store r8-12 */
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stmea r0!, {r3-r7}
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#elif defined(CONFIG_ARMV7_M)
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stmia r0, {v1-v8, ip}
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#ifdef CONFIG_FP_SHARING
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add r0, r2, #_thread_offset_to_preempt_float
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vstmia r0, {s16-s31}
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#endif /* CONFIG_FP_SHARING */
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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/*
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* Prepare to clear PendSV with interrupts unlocked, but
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* don't clear it yet. PendSV must not be cleared until
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* the new thread is context-switched in since all decisions
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* to pend PendSV have been taken with the current kernel
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* state and this is what we're handling currently.
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*/
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ldr v4, =_SCS_ICSR
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ldr v3, =_SCS_ICSR_UNPENDSV
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/* protect the kernel state while we play with the thread lists */
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#if defined(CONFIG_ARMV6_M)
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cpsid i
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#elif defined(CONFIG_ARMV7_M)
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movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
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msr BASEPRI, r0
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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/* _kernel is still in r1 */
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/* fetch the thread to run from the ready queue cache */
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ldr r2, [r1, _kernel_offset_to_ready_q_cache]
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str r2, [r1, #_kernel_offset_to_current]
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/*
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* Clear PendSV so that if another interrupt comes in and
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* decides, with the new kernel state baseed on the new thread
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* being context-switched in, that it needs to reschedules, it
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* will take, but that previously pended PendSVs do not take,
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* since they were based on the previous kernel state and this
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* has been handled.
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*/
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/* _SCS_ICSR is still in v4 and _SCS_ICSR_UNPENDSV in v3 */
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str v3, [v4, #0]
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/* Restore previous interrupt disable state (irq_lock key) */
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ldr r0, [r2, #_thread_offset_to_basepri]
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movs.n r3, #0
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str r3, [r2, #_thread_offset_to_basepri]
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#if defined(CONFIG_ARMV6_M)
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/* BASEPRI not available, previous interrupt disable state
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* maps to PRIMASK.
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*
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* Only enable interrupts if value is 0, meaning interrupts
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* were enabled before irq_lock was called.
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*/
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cmp r0, #0
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bne _thread_irq_disabled
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cpsie i
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_thread_irq_disabled:
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ldr r4, =_thread_offset_to_callee_saved
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adds r0, r2, r4
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/* restore r4-r12 for new thread */
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/* first restore r8-r12 located after r4-r7 (4*4bytes) */
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adds r0, #16
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ldmia r0!, {r3-r7}
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/* move to correct registers */
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mov r8, r3
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mov r9, r4
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mov r10, r5
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mov r11, r6
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mov ip, r7
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/* restore r4-r7, go back 9*4 bytes to the start of the stored block */
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subs r0, #36
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ldmia r0!, {r4-r7}
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#elif defined(CONFIG_ARMV7_M)
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/* restore BASEPRI for the incoming thread */
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msr BASEPRI, r0
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#ifdef CONFIG_FP_SHARING
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add r0, r2, #_thread_offset_to_preempt_float
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vldmia r0, {s16-s31}
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#endif
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#ifdef CONFIG_MPU_STACK_GUARD
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/* r2 contains k_thread */
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add r0, r2, #0
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push {r2, lr}
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blx configure_mpu_stack_guard
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pop {r2, lr}
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#endif /* CONFIG_MPU_STACK_GUARD */
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#ifdef CONFIG_USERSPACE
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/* r2 contains k_thread */
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add r0, r2, #0
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push {r2, lr}
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blx configure_mpu_mem_domain
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pop {r2, lr}
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#endif /* CONFIG_USERSPACE */
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/* load callee-saved + psp from thread */
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add r0, r2, #_thread_offset_to_callee_saved
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ldmia r0, {v1-v8, ip}
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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msr PSP, ip
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#ifdef CONFIG_EXECUTION_BENCHMARKING
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stm sp!,{r0-r3} /* Save regs r0 to r4 on stack */
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push {lr}
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bl read_timer_end_of_swap
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#if defined(CONFIG_ARMV6_M)
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pop {r3}
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mov lr,r3
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#else
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pop {lr}
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#endif /* CONFIG_ARMV6_M */
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ldm sp!,{r0-r3} /* Load back regs ro to r4 */
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#endif /* CONFIG_EXECUTION_BENCHMARKING */
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/* exc return */
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bx lr
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#if defined(CONFIG_ARMV6_M)
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SECTION_FUNC(TEXT, __svc)
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/* Use EXC_RETURN state to find out if stack frame is on the
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* MSP or PSP
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*/
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ldr r0, =0x4
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mov r1, lr
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tst r1, r0
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beq _stack_frame_msp
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mrs r0, PSP
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bne _stack_frame_endif
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_stack_frame_msp:
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mrs r0, MSP
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_stack_frame_endif:
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/* Figure out what SVC call number was invoked */
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ldr r1, [r0, #24] /* grab address of PC from stack frame */
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/* SVC is a two-byte instruction, point to it and read encoding */
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subs r1, r1, #2
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ldrb r1, [r1, #0]
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/*
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* grab service call number:
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* 1: irq_offload (if configured)
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* 2: kernel panic or oops (software generated fatal exception)
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* Planned implementation of system calls for memory protection will
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* expand this case.
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*/
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cmp r1, #2
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beq _oops
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#if CONFIG_IRQ_OFFLOAD
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push {lr}
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blx _irq_do_offload /* call C routine which executes the offload */
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pop {r3}
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mov lr, r3
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#endif
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/* exception return is done in _IntExit() */
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b _IntExit
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_oops:
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push {lr}
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blx _do_kernel_oops
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pop {pc}
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#elif defined(CONFIG_ARMV7_M)
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/**
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*
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* @brief Service call handler
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*
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* The service call (svc) is only used in __swap() to enter handler mode so we
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* can go through the PendSV exception to perform a context switch.
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*
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* @return N/A
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*/
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SECTION_FUNC(TEXT, __svc)
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tst lr, #0x4 /* did we come from thread mode ? */
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ite eq /* if zero (equal), came from handler mode */
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mrseq r0, MSP /* handler mode, stack frame is on MSP */
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mrsne r0, PSP /* thread mode, stack frame is on PSP */
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ldr r1, [r0, #24] /* grab address of PC from stack frame */
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/* SVC is a two-byte instruction, point to it and read encoding */
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ldrh r1, [r1, #-2]
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/*
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* grab service call number:
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* 0: context switch
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* 1: irq_offload (if configured)
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* 2: kernel panic or oops (software generated fatal exception)
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* Planned implementation of system calls for memory protection will
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* expand this case.
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*/
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ands r1, #0xff
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beq _context_switch
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cmp r1, #2
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beq _oops
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#if CONFIG_IRQ_OFFLOAD
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push {lr}
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blx _irq_do_offload /* call C routine which executes the offload */
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pop {lr}
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/* exception return is done in _IntExit() */
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b _IntExit
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#endif
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_context_switch:
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/*
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* Unlock interrupts:
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* - in a SVC call, so protected against context switches
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* - allow PendSV, since it's running at prio 0xff
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*/
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eors.n r0, r0
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msr BASEPRI, r0
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/* set PENDSV bit, pending the PendSV exception */
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ldr r1, =_SCS_ICSR
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ldr r2, =_SCS_ICSR_PENDSV
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str r2, [r1, #0]
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/* handler mode exit, to PendSV */
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bx lr
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_oops:
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push {lr}
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blx _do_kernel_oops
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pop {pc}
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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/**
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*
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* @brief Initiate a cooperative context switch
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*
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* The __swap() routine is invoked by various kernel services to effect
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* a cooperative context context switch. Prior to invoking __swap(), the caller
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* disables interrupts via irq_lock() and the return 'key' is passed as a
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* parameter to __swap(). The 'key' actually represents the BASEPRI register
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* prior to disabling interrupts via the BASEPRI mechanism.
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*
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* __swap() itself does not do much.
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*
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* It simply stores the intlock key (the BASEPRI value) parameter into
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* current->basepri, and then triggers a service call exception (svc) to setup
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* the PendSV exception, which does the heavy lifting of context switching.
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* This is the only place we have to save BASEPRI since the other paths to
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* __pendsv all come from handling an interrupt, which means we know the
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* interrupts were not locked: in that case the BASEPRI value is 0.
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*
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* Given that __swap() is called to effect a cooperative context switch,
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* only the caller-saved integer registers need to be saved in the thread of the
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* outgoing thread. This is all performed by the hardware, which stores it in
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* its exception stack frame, created when handling the svc exception.
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*
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* On Cortex-M0/M0+ the intlock key is represented by the PRIMASK register,
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* as BASEPRI is not available.
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*
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* @return may contain a return value setup by a call to
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* _set_thread_return_value()
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*
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* C function prototype:
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*
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* unsigned int __swap (unsigned int basepri);
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*
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*/
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SECTION_FUNC(TEXT, __swap)
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#ifdef CONFIG_EXECUTION_BENCHMARKING
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push {lr}
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bl read_timer_start_of_swap
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#if defined(CONFIG_ARMV6_M)
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pop {r3}
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mov lr,r3
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#else
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pop {lr}
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#endif /* CONFIG_ARMV6_M */
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#endif /* CONFIG_EXECUTION_BENCHMARKING */
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ldr r1, =_kernel
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ldr r2, [r1, #_kernel_offset_to_current]
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str r0, [r2, #_thread_offset_to_basepri]
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/*
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* Set __swap()'s default return code to -EAGAIN. This eliminates the need
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* for the timeout code to set it itself.
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*/
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ldr r1, =_k_neg_eagain
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ldr r1, [r1]
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str r1, [r2, #_thread_offset_to_swap_return_value]
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#if defined(CONFIG_ARMV6_M)
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/* No priority-based interrupt masking on M0/M0+,
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* pending PendSV is used instead of svc
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*/
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ldr r1, =_SCS_ICSR
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ldr r3, =_SCS_ICSR_PENDSV
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str r3, [r1, #0]
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/* Unlock interrupts to allow PendSV, since it's running at prio 0xff
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*
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* PendSV handler will be called if there are no other interrupts
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* of a higher priority pending.
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*/
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cpsie i
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#elif defined(CONFIG_ARMV7_M)
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svc #0
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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/* coming back from exception, r2 still holds the pointer to _current */
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ldr r0, [r2, #_thread_offset_to_swap_return_value]
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bx lr
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