243 lines
6.7 KiB
ArmAsm
243 lines
6.7 KiB
ArmAsm
/*
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* Copyright (c) 2016 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arch/nios2/asm.h>
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#include <kernel_structs.h>
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#include <offsets_short.h>
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/* exports */
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GTEXT(_exception)
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/* import */
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GTEXT(_Fault)
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GTEXT(__swap)
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#ifdef CONFIG_IRQ_OFFLOAD
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GTEXT(_irq_do_offload)
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GTEXT(_offload_routine)
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#endif
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#ifdef CONFIG_TIMESLICING
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GTEXT(_update_time_slice_before_swap)
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#endif
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/* Allows use of r1/at register, otherwise reserved for assembler use */
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.set noat
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/* Placed into special 'exception' section so that the linker can put this code
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* at ALT_CPU_EXCEPTION_ADDR defined in system.h
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*
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* This is the common entry point for processor exceptions and interrupts from
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* the Internal Interrupt Controller (IIC).
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*
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* If the External (EIC) controller is in use, then we will never get here on
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* behalf of an interrupt, instead the EIC driver will have set up a vector
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* table and the processor will jump directly into the appropriate table
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* entry.
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*/
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SECTION_FUNC(exception.entry, _exception)
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/* Reserve thread stack space for saving context */
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subi sp, sp, __NANO_ESF_SIZEOF
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/* Preserve all caller-saved registers onto the thread's stack */
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stw ra, __NANO_ESF_ra_OFFSET(sp)
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stw r1, __NANO_ESF_r1_OFFSET(sp)
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stw r2, __NANO_ESF_r2_OFFSET(sp)
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stw r3, __NANO_ESF_r3_OFFSET(sp)
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stw r4, __NANO_ESF_r4_OFFSET(sp)
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stw r5, __NANO_ESF_r5_OFFSET(sp)
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stw r6, __NANO_ESF_r6_OFFSET(sp)
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stw r7, __NANO_ESF_r7_OFFSET(sp)
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stw r8, __NANO_ESF_r8_OFFSET(sp)
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stw r9, __NANO_ESF_r9_OFFSET(sp)
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stw r10, __NANO_ESF_r10_OFFSET(sp)
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stw r11, __NANO_ESF_r11_OFFSET(sp)
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stw r12, __NANO_ESF_r12_OFFSET(sp)
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stw r13, __NANO_ESF_r13_OFFSET(sp)
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stw r14, __NANO_ESF_r14_OFFSET(sp)
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stw r15, __NANO_ESF_r15_OFFSET(sp)
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/* Store value of estatus control register */
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rdctl et, estatus
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stw et, __NANO_ESF_estatus_OFFSET(sp)
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/* ea-4 is the address of the instruction when the exception happened,
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* put this in the stack frame as well
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*/
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addi r15, ea, -4
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stw r15, __NANO_ESF_instr_OFFSET(sp)
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/* Figure out whether we are here because of an interrupt or an
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* exception. If an interrupt, switch stacks and enter IRQ handling
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* code. If an exception, remain on current stack and enter exception
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* handing code. From the CPU manual, ipending must be nonzero and
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* estatis.PIE must be enabled for this to be considered an interrupt.
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*
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* Stick ipending in r4 since it will be an arg for _enter_irq
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*/
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rdctl r4, ipending
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beq r4, zero, not_interrupt
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/* We stashed estatus in et earlier */
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andi r15, et, 1
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beq r15, zero, not_interrupt
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is_interrupt:
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/* If we get here, this is an interrupt */
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/* Grab a reference to _kernel in r10 so we can determine the
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* current irq stack pointer
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*/
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movhi r10, %hi(_kernel)
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ori r10, r10, %lo(_kernel)
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/* Stash a copy of thread's sp in r12 so that we can put it on the IRQ
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* stack
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*/
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mov r12, sp
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/* Switch to interrupt stack */
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ldw sp, _kernel_offset_to_irq_stack(r10)
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/* Store thread stack pointer onto IRQ stack */
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addi sp, sp, -4
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stw r12, 0(sp)
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on_irq_stack:
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/* Enter C interrupt handling code. Value of ipending will be the
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* function parameter since we put it in r4
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*/
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call _enter_irq
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/* Interrupt handler finished and the interrupt should be serviced
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* now, the appropriate bits in ipending should be cleared */
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/* Get a reference to _kernel again in r10 */
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movhi r10, %hi(_kernel)
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ori r10, r10, %lo(_kernel)
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#ifdef CONFIG_PREEMPT_ENABLED
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ldw r11, _kernel_offset_to_current(r10)
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/* Determine whether the exception of the ISR requires context
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* switch
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*/
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/*
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* Non-preemptible thread ? Do not schedule (see explanation of
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* preempt field in kernel_struct.h).
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*/
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ldhu r12, _thread_offset_to_preempt(r11)
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movui r3, _NON_PREEMPT_THRESHOLD
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bgeu r12, r3, no_reschedule
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/* Call into the kernel to see if a scheduling decision is necessary */
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ldw r2, _kernel_offset_to_ready_q_cache(r10)
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beq r2, r11, no_reschedule
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/*
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* A context reschedule is required: keep the volatile registers of
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* the interrupted thread on the context's stack. Utilize
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* the existing __swap() primitive to save the remaining
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* thread's registers (including floating point) and perform
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* a switch to the new thread.
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*/
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/* We put the thread stack pointer on top of the IRQ stack before
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* we switched stacks. Restore it to go back to thread stack
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*/
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ldw sp, 0(sp)
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#ifdef CONFIG_TIMESLICING
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call _update_time_slice_before_swap
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#endif
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/* Argument to Swap() is estatus since that's the state of the
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* status register before the exception happened. When coming
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* out of the context switch we need this info to restore
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* IRQ lock state. We put this value in et earlier.
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*/
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mov r4, et
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call __swap
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jmpi _exception_exit
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#else
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jmpi no_reschedule
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#endif /* CONFIG_PREEMPT_ENABLED */
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not_interrupt:
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/* Since this wasn't an interrupt we're not going to restart the
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* faulting instruction.
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*
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* We earlier put ea - 4 in the stack frame, replace it with just ea
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*/
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stw ea, __NANO_ESF_instr_OFFSET(sp)
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#ifdef CONFIG_IRQ_OFFLOAD
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/* Check the contents of _offload_routine. If non-NULL, jump into
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* the interrupt code anyway.
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*/
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movhi r10, %hi(_offload_routine)
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ori r10, r10, %lo(_offload_routine)
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ldw r11, (r10)
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bne r11, zero, is_interrupt
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#endif
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_exception_enter_fault:
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/* If we get here, the exception wasn't in interrupt or an
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* invocation of irq_oflload(). Let _Fault() handle it in
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* C domain
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*/
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mov r4, sp
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call _Fault
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jmpi _exception_exit
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no_reschedule:
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/* We put the thread stack pointer on top of the IRQ stack before
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* we switched stacks. Restore it to go back to thread stack
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*/
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ldw sp, 0(sp)
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/* Fall through */
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_exception_exit:
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/* We are on the thread stack. Restore all saved registers
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* and return to the interrupted context */
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/* Return address from the exception */
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ldw ea, __NANO_ESF_instr_OFFSET(sp)
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/* Restore estatus
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* XXX is this right??? */
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ldw r5, __NANO_ESF_estatus_OFFSET(sp)
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wrctl estatus, r5
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/* Restore caller-saved registers */
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ldw ra, __NANO_ESF_ra_OFFSET(sp)
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ldw r1, __NANO_ESF_r1_OFFSET(sp)
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ldw r2, __NANO_ESF_r2_OFFSET(sp)
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ldw r3, __NANO_ESF_r3_OFFSET(sp)
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ldw r4, __NANO_ESF_r4_OFFSET(sp)
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ldw r5, __NANO_ESF_r5_OFFSET(sp)
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ldw r6, __NANO_ESF_r6_OFFSET(sp)
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ldw r7, __NANO_ESF_r7_OFFSET(sp)
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ldw r8, __NANO_ESF_r8_OFFSET(sp)
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ldw r9, __NANO_ESF_r9_OFFSET(sp)
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ldw r10, __NANO_ESF_r10_OFFSET(sp)
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ldw r11, __NANO_ESF_r11_OFFSET(sp)
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ldw r12, __NANO_ESF_r12_OFFSET(sp)
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ldw r13, __NANO_ESF_r13_OFFSET(sp)
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ldw r14, __NANO_ESF_r14_OFFSET(sp)
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ldw r15, __NANO_ESF_r15_OFFSET(sp)
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/* Put the stack pointer back where it was when we entered
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* exception state
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*/
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addi sp, sp, __NANO_ESF_SIZEOF
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/* All done, copy estatus into status and transfer to ea */
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eret
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