74 lines
2.2 KiB
C
74 lines
2.2 KiB
C
/*
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* Copyright (c) 2021 Katsuhiro Suzuki
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SIFIVE_FU740_PRCI_H
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#define _SIFIVE_FU740_PRCI_H
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#define Z_REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
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#define PRCI_REG(offset) Z_REG32(PRCI_BASE_ADDR, offset)
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/* Register offsets */
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#define PRCI_HFXOSCCFG (0x0000)
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#define PRCI_COREPLLCFG (0x0004)
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#define PRCI_COREPLLOUTDIV (0x0008)
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#define PRCI_DDRPLLCFG (0x000c)
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#define PRCI_DDRPLLOUTDIV (0x0010)
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#define PRCI_GEMGXLPLLCFG (0x001c)
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#define PRCI_GEMGXLPLLOUTDIV (0x0020)
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#define PRCI_CORECLKSEL (0x0024)
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#define PRCI_DEVICESRESETN (0x0028)
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#define PRCI_CLKMUXSTATUS (0x002c)
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#define PRCI_COREPLLSEL (0x0040)
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#define PRCI_HFPCLKPLLCFG (0x0050)
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#define PRCI_HFPCLKPLLOUTDIV (0x0054)
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#define PRCI_HFPCLKPLLSEL (0x0058)
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#define PLL_R(x) (((x) & 0x3f) << 0)
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#define PLL_F(x) (((x) & 0x1ff) << 6)
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#define PLL_Q(x) (((x) & 0x7) << 15)
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#define PLL_RANGE(x) (((x) & 0x7) << 18)
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#define PLL_BYPASS(x) (((x) & 0x1) << 24)
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#define PLL_FSE(x) (((x) & 0x1) << 25)
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#define PLL_LOCK(x) (((x) & 0x1) << 31)
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#define PLL_RANGE_RESET 0
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#define PLL_RANGE_0MHZ 1
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#define PLL_RANGE_11MHZ 2
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#define PLL_RANGE_18MHZ 3
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#define PLL_RANGE_30MHZ 4
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#define PLL_RANGE_50MHZ 5
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#define PLL_RANGE_80MHZ 6
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#define PLL_RANGE_130MHZ 7
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#define PLL_BYPASS_DISABLE 0
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#define PLL_BYPASS_ENABLE 1
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#define PLL_FSE_INTERNAL 1
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#define OUTDIV_PLLCKE(x) (((x) & 0x1) << 31)
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#define OUTDIV_PLLCKE_DIS 0
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#define OUTDIV_PLLCKE_ENA 1
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#define CLKSEL_SEL(x) (((x) & 0x1) << 0)
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#define CLKSEL_PLL 0
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#define CLKSEL_HFCLK 1
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#define CLKMUXSTATUS_CORECLKPLLSEL_OFF 0
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#define CLKMUXSTATUS_TLCLKSEL_OFF 1
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#define CLKMUXSTATUS_RTCXSEL_OFF 2
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#define CLKMUXSTATUS_DDRCTRLCLKSEL_OFF 3
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#define CLKMUXSTATUS_DDRPHYCLKSEL_OFF 4
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#define CLKMUXSTATUS_GEMGXLCLKSEL_OFF 6
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#define CLKMUXSTATUS_MAINMEMCLKSEL_OFF 7
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#define COREPLLSEL_SEL(x) (((x) & 0x1) << 0)
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#define COREPLLSEL_COREPLL 0
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#define COREPLLSEL_DVFSCOREPLL 1
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#endif /* _SIFIVE_FU740_PRCI_H */
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