46 lines
1011 B
C
46 lines
1011 B
C
/* soc.c - system/hardware module for nsim */
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/*
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* Copyright (c) 2016, 2019 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* This module provides routines to initialize and support board-level hardware
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* for the ARC EM and HS cores in nSIM simulator.
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*
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*/
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include "soc.h"
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#ifdef CONFIG_SMP
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static int arc_nsim_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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uint32_t core;
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uint32_t i;
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/* allocate all IDU interrupts to master core */
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core = z_arc_v2_core_id();
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z_arc_connect_idu_disable();
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for (i = 0; i < (CONFIG_NUM_IRQS - ARC_CONNECT_IDU_IRQ_START); i++) {
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z_arc_connect_idu_set_mode(i, ARC_CONNECT_INTRPT_TRIGGER_LEVEL,
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ARC_CONNECT_DISTRI_MODE_ROUND_ROBIN);
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z_arc_connect_idu_set_dest(i, 1 << core);
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z_arc_connect_idu_set_mask(i, 0x0);
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}
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z_arc_connect_idu_enable();
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return 0;
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}
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SYS_INIT(arc_nsim_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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#endif /* CONFIG_SMP */
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