710 lines
15 KiB
Plaintext
710 lines
15 KiB
Plaintext
/*
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* Copyright (c) 2020 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "skeleton.dtsi"
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#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/pcie/pcie.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "intel,elkhart_lake";
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d-cache-line-size = <64>;
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reg = <0>;
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};
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};
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dram0: memory@0 {
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device_type = "memory";
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reg = <0x0 DT_DRAM_SIZE>;
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};
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ibecc: ibecc {
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compatible = "intel,ibecc";
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label = "ibecc";
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status = "okay";
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};
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intc: ioapic@fec00000 {
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compatible = "intel,ioapic";
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reg = <0xfec00000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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pcie0 {
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label = "PCIE_0";
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "intel,pcie";
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ranges;
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ptm_root0: ptm_root@e000 {
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compatible = "ptm-root";
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reg = <PCIE_BDF(0,0x1c,0) PCIE_ID(0x8086,0x4b38)>;
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label = "PTM_ROOT_0";
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status = "okay";
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};
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uart0: uart@f000 {
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compatible = "ns16550";
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reg = <PCIE_BDF(0,0x1e,0) PCIE_ID(0x8086,0x4b28)>;
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reg-shift = <2>;
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label = "UART_0";
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clock-frequency = <1843200>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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status = "okay";
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current-speed = <115200>;
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};
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uart1: uart@f100 {
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compatible = "ns16550";
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reg = <PCIE_BDF(0,0x1e,1) PCIE_ID(0x8086,0x4b29)>;
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reg-shift = <2>;
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label = "UART_1";
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clock-frequency = <1843200>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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status = "okay";
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current-speed = <115200>;
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};
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uart2: uart@ca00 {
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compatible = "ns16550";
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reg = <PCIE_BDF(0,0x19,2) PCIE_ID(0x8086,0x4b4d)>;
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reg-shift = <2>;
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label = "UART_2";
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clock-frequency = <1843200>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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status = "okay";
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current-speed = <115200>;
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};
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uart_pse_0: uart@8800 {
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compatible = "ns16550";
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reg = <PCIE_BDF(0,0x11,0) PCIE_ID(0x8086,0x4b96)>;
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reg-shift = <2>;
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label = "UART_PSE_0";
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clock-frequency = <1843200>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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status = "disabled";
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current-speed = <115200>;
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};
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uart_pse_1: uart@8900 {
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compatible = "ns16550";
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reg = <PCIE_BDF(0,0x11,1) PCIE_ID(0x8086,0x4b97)>;
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reg-shift = <2>;
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label = "UART_PSE_1";
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clock-frequency = <1843200>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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status = "disabled";
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current-speed = <115200>;
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};
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uart_pse_2: uart@8a00 {
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compatible = "ns16550";
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reg = <PCIE_BDF(0,0x11,2) PCIE_ID(0x8086,0x4b98)>;
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reg-shift = <2>;
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label = "UART_PSE_2";
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clock-frequency = <1843200>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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status = "disabled";
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current-speed = <115200>;
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};
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uart_pse_3: uart@8b00 {
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compatible = "ns16550";
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reg = <PCIE_BDF(0,0x11,3) PCIE_ID(0x8086,0x4b99)>;
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reg-shift = <2>;
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label = "UART_PSE_3";
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clock-frequency = <1843200>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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status = "disabled";
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current-speed = <115200>;
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};
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uart_pse_4: uart@8c00 {
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compatible = "ns16550";
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reg = <PCIE_BDF(0,0x11,4) PCIE_ID(0x8086,0x4b9a)>;
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reg-shift = <2>;
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label = "UART_PSE_4";
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clock-frequency = <1843200>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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status = "disabled";
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current-speed = <115200>;
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};
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uart_pse_5: uart@8d00 {
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compatible = "ns16550";
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reg = <PCIE_BDF(0,0x11,5) PCIE_ID(0x8086,0x4b9b)>;
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reg-shift = <2>;
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label = "UART_PSE_5";
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clock-frequency = <1843200>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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status = "disabled";
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current-speed = <115200>;
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};
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i2c0: i2c@a800 {
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compatible = "snps,designware-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <PCIE_BDF(0,0x15,0) PCIE_ID(0x8086,0x4b78)>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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label = "I2C_0";
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status = "okay";
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};
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i2c1: i2c@a900 {
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compatible = "snps,designware-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <PCIE_BDF(0,0x15,1) PCIE_ID(0x8086,0x4b79)>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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label = "I2C_1";
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status = "okay";
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};
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i2c2: i2c@aa00 {
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compatible = "snps,designware-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <PCIE_BDF(0,0x15,2) PCIE_ID(0x8086,0x4b7a)>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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label = "I2C_2";
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status = "okay";
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};
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i2c3: i2c@ab00 {
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compatible = "snps,designware-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <PCIE_BDF(0,0x15,3) PCIE_ID(0x8086,0x4b7b)>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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label = "I2C_3";
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status = "okay";
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};
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i2c4: i2c@c800 {
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compatible = "snps,designware-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <PCIE_BDF(0,0x19,0) PCIE_ID(0x8086,0x4b4b)>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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label = "I2C_4";
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status = "okay";
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};
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i2c5: i2c@c900 {
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compatible = "snps,designware-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <PCIE_BDF(0,0x19,1) PCIE_ID(0x8086,0x4b4c)>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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label = "I2C_5";
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status = "okay";
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};
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i2c6: i2c@8000 {
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compatible = "snps,designware-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <PCIE_BDF(0,0x10,0) PCIE_ID(0x8086,0x4b44)>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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label = "I2C_6";
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status = "okay";
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};
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i2c7: i2c@8100 {
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compatible = "snps,designware-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <PCIE_BDF(0,0x10,1) PCIE_ID(0x8086,0x4b45)>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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label = "I2C_7";
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status = "okay";
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};
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i2c_pse_0: i2c@d800 {
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compatible = "snps,designware-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <PCIE_BDF(0,0x1b,0) PCIE_ID(0x8086,0x4bb9)>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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label = "I2C_PSE_0";
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status = "okay";
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};
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i2c_pse_1: i2c@d900 {
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compatible = "snps,designware-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <PCIE_BDF(0,0x1b,1) PCIE_ID(0x8086,0x4bba)>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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label = "I2C_PSE_1";
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status = "okay";
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};
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i2c_pse_2: i2c@da00 {
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compatible = "snps,designware-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <PCIE_BDF(0,0x1b,2) PCIE_ID(0x8086,0x4bbb)>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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label = "I2C_PSE_2";
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status = "okay";
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};
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i2c_pse_3: i2c@db00 {
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compatible = "snps,designware-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <PCIE_BDF(0,0x1b,3) PCIE_ID(0x8086,0x4bbc)>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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label = "I2C_PSE_3";
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status = "okay";
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};
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i2c_pse_4: i2c@dc00 {
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compatible = "snps,designware-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <PCIE_BDF(0,0x1b,4) PCIE_ID(0x8086,0x4bbd)>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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label = "I2C_PSE_4";
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status = "okay";
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};
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i2c_pse_5: i2c@dd00 {
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compatible = "snps,designware-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <PCIE_BDF(0,0x1b,5) PCIE_ID(0x8086,0x4bbe)>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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label = "I2C_PSE_5";
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status = "okay";
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};
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i2c_pse_6: i2c@de00 {
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compatible = "snps,designware-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <PCIE_BDF(0,0x1b,6) PCIE_ID(0x8086,0x4bbf)>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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label = "I2C_PSE_6";
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status = "okay";
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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vtd: vtd@fed91000 {
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compatible = "intel,vt-d";
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label = "VTD_0";
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reg = <0xfed91000 0x1000>;
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status = "okay";
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};
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uart1_fixed: uart@fe040000 {
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compatible = "ns16550";
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reg = <0xfe040000 0x1000>;
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reg-shift = <0>;
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label = "UART_1_FIXED";
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clock-frequency = <1843200>;
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interrupts = <3 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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status = "disabled";
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current-speed = <115200>;
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};
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uart2_fixed: uart@fe042000 {
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compatible = "ns16550";
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reg = <0xfe042000 0x1000>;
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reg-shift = <0>;
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label = "UART_2_FIXED";
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clock-frequency = <1843200>;
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interrupts = <4 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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status = "disabled";
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current-speed = <115200>;
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};
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gpio_0_b: gpio@fd6e0700 {
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compatible = "intel,gpio";
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reg = <0xfd6e0700 0x1000>;
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interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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label = "GPIO_COM_0_B";
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group-index = <0x0>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <24>;
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pin-offset = <0>;
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status = "okay";
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};
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gpio_0_t: gpio@fd6e08a0 {
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compatible = "intel,gpio";
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reg = <0xfd6e08a0 0x1000>;
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interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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label = "GPIO_COM_0_T";
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group-index = <0x1>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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pin-offset = <26>;
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status = "okay";
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};
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gpio_0_g: gpio@fd6e09a0 {
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compatible = "intel,gpio";
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reg = <0xfd6e09a0 0x1000>;
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interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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label = "GPIO_COM_0_G";
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group-index = <0x2>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <24>;
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pin-offset = <42>;
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status = "okay";
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};
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gpio_1_v: gpio@fd6d0700 {
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compatible = "intel,gpio";
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reg = <0xfd6d0700 0x1000>;
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interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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label = "GPIO_COM_1_V";
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group-index = <0x0>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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pin-offset = <0>;
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
gpio_1_h: gpio@fd6d0800 {
|
|
compatible = "intel,gpio";
|
|
reg = <0xfd6d0800 0x1000>;
|
|
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
|
|
interrupt-parent = <&intc>;
|
|
|
|
label = "GPIO_COM_1_H";
|
|
group-index = <0x1>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
ngpios = <24>;
|
|
pin-offset = <16>;
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
gpio_1_d: gpio@fd6d0980 {
|
|
compatible = "intel,gpio";
|
|
reg = <0xfd6d0980 0x1000>;
|
|
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
|
|
interrupt-parent = <&intc>;
|
|
|
|
label = "GPIO_COM_1_D";
|
|
group-index = <0x2>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
ngpios = <20>;
|
|
pin-offset = <40>;
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
gpio_1_u: gpio@fd6d0ad0 {
|
|
compatible = "intel,gpio";
|
|
reg = <0xfd6d0ad0 0x1000>;
|
|
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
|
|
interrupt-parent = <&intc>;
|
|
|
|
label = "GPIO_COM_1_U";
|
|
group-index = <0x3>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
ngpios = <20>;
|
|
pin-offset = <61>;
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
gpio_1_vG: gpio@fd6d0c50 {
|
|
compatible = "intel,gpio";
|
|
reg = <0xfd6d0c50 0x1000>;
|
|
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
|
|
interrupt-parent = <&intc>;
|
|
|
|
label = "GPIO_COM_1_vG";
|
|
group-index = <0x4>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
ngpios = <28>;
|
|
pin-offset = <85>;
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
gpio_3_s: gpio@fd6b0810 {
|
|
compatible = "intel,gpio";
|
|
reg = <0xfd6b0810 0x1000>;
|
|
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
|
|
interrupt-parent = <&intc>;
|
|
|
|
label = "GPIO_COM_3_S";
|
|
group-index = <0x1>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
ngpios = <2>;
|
|
pin-offset = <17>;
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
gpio_3_a: gpio@fd6b0830 {
|
|
compatible = "intel,gpio";
|
|
reg = <0xfd6b0830 0x1000>;
|
|
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
|
|
interrupt-parent = <&intc>;
|
|
|
|
label = "GPIO_COM_3_A";
|
|
group-index = <0x2>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
ngpios = <24>;
|
|
pin-offset = <25>;
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
gpio_3_vG: gpio@fd6b09b0 {
|
|
compatible = "intel,gpio";
|
|
reg = <0xfd6b09b0 0x1000>;
|
|
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
|
|
interrupt-parent = <&intc>;
|
|
|
|
label = "GPIO_COM_3_vG";
|
|
group-index = <0x3>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
ngpios = <4>;
|
|
pin-offset = <49>;
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
gpio_4_c: gpio@fd6a0700 {
|
|
compatible = "intel,gpio";
|
|
reg = <0xfd6a0700 0x1000>;
|
|
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
|
|
interrupt-parent = <&intc>;
|
|
|
|
label = "GPIO_COM_4_C";
|
|
group-index = <0x0>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
ngpios = <24>;
|
|
pin-offset = <0>;
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
gpio_4_f: gpio@fd6a0880 {
|
|
compatible = "intel,gpio";
|
|
reg = <0xfd6a0880 0x1000>;
|
|
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
|
|
interrupt-parent = <&intc>;
|
|
|
|
label = "GPIO_COM_4_F";
|
|
group-index = <0x1>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
ngpios = <24>;
|
|
pin-offset = <24>;
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
gpio_4_e: gpio@fd6a0a70 {
|
|
compatible = "intel,gpio";
|
|
reg = <0xfd6a0a70 0x1000>;
|
|
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
|
|
interrupt-parent = <&intc>;
|
|
|
|
label = "GPIO_COM_4_E";
|
|
group-index = <0x3>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
ngpios = <24>;
|
|
pin-offset = <57>;
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
gpio_5_r: gpio@fd690700 {
|
|
compatible = "intel,gpio";
|
|
reg = <0xfd690700 0x1000>;
|
|
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
|
|
interrupt-parent = <&intc>;
|
|
|
|
label = "GPIO_COM_5_R";
|
|
group-index = <0x0>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
ngpios = <8>;
|
|
pin-offset = <0>;
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
hpet: hpet@fed00000 {
|
|
label = "HPET";
|
|
compatible = "intel,hpet";
|
|
reg = <0xfed00000 0x400>;
|
|
interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>;
|
|
interrupt-parent = <&intc>;
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
counter: counter@70 {
|
|
label = "CMOS";
|
|
compatible = "motorola,mc146818";
|
|
reg = <0x70 0x0D 0x71 0x0D>;
|
|
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|