zephyr/dts/bindings/qspi/st,stm32-qspi.yaml

64 lines
1.6 KiB
YAML

# Copyright (c) 2020, Linaro limited
# SPDX-License-Identifier: Apache-2.0
description: |
STM32 QSPI device representation. A stm32 quadspi node would typically
looks to this:
&quadspi {
pinctrl-0 = <&quadspi_clk_pe10 &quadspi_ncs_pe11
&quadspi_bk1_io0_pe12 &quadspi_bk1_io1_pe13
&quadspi_bk1_io2_pe14 &quadspi_bk1_io3_pe15>;
dmas = <&dma1 5 5 0x0000 0x03>;
dma-names = "tx_rx";
status = "okay";
};
compatible: "st,stm32-qspi"
include: [base.yaml, pinctrl-device.yaml]
bus: qspi
properties:
reg:
required: true
interrupts:
required: true
pinctrl-0:
required: true
pinctrl-names:
required: true
dmas:
description: |
Optional DMA channel specifier. If DMA should be used, specifier should
hold a phandle reference to the dma controller, the channel number,
the slot number, channel configuration and finally features.
For example dmas for TX/RX on QSPI
dmas = <&dma1 5 5 0x0000 0x03>;
dma-names:
description: |
DMA channel name. If DMA should be used, expected value is "tx_rx".
For example
dma-names = "tx_rx";
flash-id:
type: int
required: false
description: |
FLash ID number. This number, if defined, helps to select the right
QSPI GPIO banks (defined as 'quadspi_bk[12]' in pinctrl property)
to communicate with flash memory.
For example
flash-id = <2>;